From 766a039ffe516929d6d311e4aff41c79584f3cac Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Sun, 26 Feb 2012 16:19:50 -0800 Subject: [PATCH] small changes to the dtlb arbiter --- rocket/src/main/scala/cpu.scala | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/rocket/src/main/scala/cpu.scala b/rocket/src/main/scala/cpu.scala index 84c33fcf..419bb315 100644 --- a/rocket/src/main/scala/cpu.scala +++ b/rocket/src/main/scala/cpu.scala @@ -41,17 +41,22 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal) val dtlbchosen = Reg(resetVal=Bits(DTLB_CPU,log2up(3))) when( dtlb.io.cpu_req.ready && dtlbarb.io.out.valid ) { dtlbchosen := dtlbarb.io.chosen } + // tlb respones come out a cycle later val chosen_vec = dtlbchosen === Bits(DTLB_VEC) val chosen_pf = dtlbchosen === Bits(DTLB_VPF) val chosen_cpu = dtlbchosen === Bits(DTLB_CPU) - // vector prefetch doesn't care about exceptions - // and shouldn't cause any anyways + dtlbarb.io.in(DTLB_VEC) <> vu.io.vec_tlb_req + vu.io.vec_tlb_resp.xcpt_ld := chosen_vec && dtlb.io.cpu_resp.xcpt_ld vu.io.vec_tlb_resp.xcpt_st := chosen_vec && dtlb.io.cpu_resp.xcpt_st vu.io.vec_tlb_resp.miss := chosen_vec && dtlb.io.cpu_resp.miss vu.io.vec_tlb_resp.ppn := dtlb.io.cpu_resp.ppn + // vector prefetch doesn't care about exceptions + // and shouldn't cause any anyways + dtlbarb.io.in(DTLB_VPF) <> vu.io.vec_pftlb_req + vu.io.vec_pftlb_resp.xcpt_ld := Bool(false) vu.io.vec_pftlb_resp.xcpt_st := Bool(false) vu.io.vec_pftlb_resp.miss := chosen_pf && dtlb.io.cpu_resp.miss @@ -69,10 +74,6 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal) ctrl.io.xcpt_dtlb_st := chosen_cpu && dtlb.io.cpu_resp.xcpt_st ctrl.io.dtlb_miss := chosen_cpu && dtlb.io.cpu_resp.miss - dtlbarb.io.in(DTLB_VEC) <> vu.io.vec_tlb_req - dtlbarb.io.in(DTLB_VPF) <> vu.io.vec_pftlb_req - - dtlb.io.cpu_req <> dtlbarb.io.out } else