riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Cleanup testing rv64uf

Browse Source
This commit is contained in:
Henry Cook 2015-07-13 18:56:18 -07:00
parent 186e32a546
commit 76046c52fe
2 changed files with 11 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/main/scala/Configs.scala
View File

@ -80,10 +80,9 @@ class DefaultConfig extends ChiselConfig (
Module(new L2BroadcastHub, { case InnerTLId => "L1ToL2"; case OuterTLId => "L2ToMC" }) Module(new L2BroadcastHub, { case InnerTLId => "L1ToL2"; case OuterTLId => "L2ToMC" })
//Tile Constants //Tile Constants
case BuildTiles => { case BuildTiles => {
TestGeneration.addSuites(rv64.map(_("p")) ++ rv64u.map(_("pt")) ++ List(bmarks)) TestGeneration.addSuites(rv64i.map(_("p")))
if(site(UseVM)) TestGeneration.addSuites(rv64u.map(_("v"))) TestGeneration.addSuites((if(site(UseVM)) List("pt","v") else List("pt")).flatMap(env => rv64u.map(_(env))))
if(!site(FDivSqrt)) TestGeneration.addSuites(List(rv64ufNoDiv("p"), rv64ufNoDiv("pt"))) TestGeneration.addSuites(if(site(NTiles) > 1) List(mtBmarks, bmarks) else List(bmarks))
if(site(NTiles) > 1) TestGeneration.addSuite(mtBmarks)
List.fill(site(NTiles)){ (r:Bool) => Module(new RocketTile(resetSignal = r), {case TLId => "L1ToL2"}) } List.fill(site(NTiles)){ (r:Bool) => Module(new RocketTile(resetSignal = r), {case TLId => "L1ToL2"}) }
} }
case BuildRoCC => None case BuildRoCC => None
@ -98,7 +97,12 @@ class DefaultConfig extends ChiselConfig (
case FastMulDiv => true case FastMulDiv => true
case XLen => 64 case XLen => 64
case NMultXpr => 32 case NMultXpr => 32
case BuildFPU => Some(() => Module(new FPU)) case BuildFPU => {
val env = if(site(UseVM)) List("p","pt","v") else List("p","pt")
if(site(FDivSqrt)) TestGeneration.addSuites(env.map(rv64uf))
else TestGeneration.addSuites(env.map(rv64ufNoDiv))
Some(() => Module(new FPU))
}
case FDivSqrt => true case FDivSqrt => true
case SFMALatency => 2 case SFMALatency => 2
case DFMALatency => 3 case DFMALatency => 3

4
src/main/scala/Testing.scala
View File

@ -106,8 +106,8 @@ object DefaultTestSuites {
// TODO: "rv64ui-pm-lrsc", "rv64mi-pm-ipi", // TODO: "rv64ui-pm-lrsc", "rv64mi-pm-ipi",
val rv64u = List(rv64ui, rv64um, rv64ua, rv64uf) val rv64u = List(rv64ui, rv64um, rv64ua)
val rv64 = rv64u ++ List(rv64si, rv64mi) val rv64i = List(rv64ui, rv64si, rv64mi)
val bmarks = new BenchmarkTestSuite("basic", "$(base_dir)/riscv-tools/riscv-tests/benchmarks", Set( val bmarks = new BenchmarkTestSuite("basic", "$(base_dir)/riscv-tools/riscv-tests/benchmarks", Set(
"median", "multiply", "qsort", "towers", "vvadd", "mm", "dhrystone", "spmv", "mt-vvadd", "mt-matmul")) "median", "multiply", "qsort", "towers", "vvadd", "mm", "dhrystone", "spmv", "mt-vvadd", "mt-matmul"))