implement NASTI Interconnect generating from configuration address map
This commit is contained in:
Howard Mao
parent
b046c57284
commit
75ec7529af
@ -1,13 +1,20 @@
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// See LICENSE for license details.
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/// See LICENSE for license details.
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package junctions
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import Chisel._
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import scala.math.max
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import scala.collection.mutable.ArraySeq
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import scala.collection.mutable.HashMap
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case object MMIOBase extends Field[BigInt]
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case object NASTIDataBits extends Field[Int]
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case object NASTIAddrBits extends Field[Int]
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case object NASTIIdBits extends Field[Int]
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object bigIntPow2 {
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def apply(in: BigInt): Boolean = in > 0 && ((in & (in-1)) == 0)
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}
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trait NASTIParameters extends UsesParameters {
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val nastiXDataBits = params(NASTIDataBits)
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val nastiWStrobeBits = nastiXDataBits / 8
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@ -149,3 +156,395 @@ class MemIONASTISlaveIOConverter(cacheBlockOffsetBits: Int) extends MIFModule wi
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io.nasti.r.bits.resp := UInt(0)
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io.mem.resp.ready := io.nasti.r.ready
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}
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class NASTIArbiter(val arbN: Int) extends NASTIModule {
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val io = new Bundle {
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val master = Vec.fill(arbN) { new NASTISlaveIO }
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val slave = new NASTIMasterIO
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}
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if (arbN > 1) {
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val arbIdBits = log2Up(arbN)
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val ar_arb = Module(new RRArbiter(new NASTIReadAddressChannel, arbN))
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val aw_arb = Module(new RRArbiter(new NASTIWriteAddressChannel, arbN))
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val slave_r_arb_id = io.slave.r.bits.id(arbIdBits - 1, 0)
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val slave_b_arb_id = io.slave.b.bits.id(arbIdBits - 1, 0)
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val w_chosen = Reg(UInt(width = arbIdBits))
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val w_done = Reg(init = Bool(true))
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when (aw_arb.io.out.fire()) {
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w_chosen := aw_arb.io.chosen
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w_done := Bool(false)
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}
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when (io.slave.w.fire() && io.slave.w.bits.last) {
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w_done := Bool(true)
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}
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for (i <- 0 until arbN) {
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val m_ar = io.master(i).ar
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val m_aw = io.master(i).aw
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val m_r = io.master(i).r
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val m_b = io.master(i).b
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val a_ar = ar_arb.io.in(i)
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val a_aw = aw_arb.io.in(i)
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val m_w = io.master(i).w
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a_ar <> m_ar
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a_ar.bits.id := Cat(m_ar.bits.id, UInt(i, arbIdBits))
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a_aw <> m_aw
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a_aw.bits.id := Cat(m_aw.bits.id, UInt(i, arbIdBits))
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m_r.valid := io.slave.r.valid && slave_r_arb_id === UInt(i)
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m_r.bits := io.slave.r.bits
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m_r.bits.id := io.slave.r.bits.id >> UInt(arbIdBits)
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m_b.valid := io.slave.b.valid && slave_b_arb_id === UInt(i)
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m_b.bits := io.slave.b.bits
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m_b.bits.id := io.slave.b.bits.id >> UInt(arbIdBits)
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m_w.ready := io.slave.w.ready && w_chosen === UInt(i) && !w_done
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}
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io.slave.r.ready := io.master(slave_r_arb_id).r.ready
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io.slave.b.ready := io.master(slave_b_arb_id).b.ready
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io.slave.w.bits := io.master(w_chosen).w.bits
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io.slave.w.valid := io.master(w_chosen).w.valid && !w_done
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io.slave.ar <> ar_arb.io.out
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io.slave.aw <> aw_arb.io.out
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aw_arb.io.out.ready := io.slave.aw.ready && w_done
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} else { io.slave <> io.master.head }
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}
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// TODO: More efficient implementation a/la Chisel Stdlib
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class NASTIReadDataArbiter(arbN: Int) extends NASTIModule {
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val io = new Bundle {
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val in = Vec.fill(arbN) { Decoupled(new NASTIReadDataChannel) }.flip
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val out = Decoupled(new NASTIReadDataChannel)
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}
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def rotateLeft[T <: Data](norm: Vec[T], rot: UInt): Vec[T] = {
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val n = norm.size
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Vec.tabulate(n) { i =>
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Mux(rot < UInt(n - i), norm(UInt(i) + rot), norm(rot - UInt(n - i)))
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}
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}
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val lockIdx = Reg(init = UInt(0, log2Up(arbN)))
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val locked = Reg(init = Bool(false))
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// use rotation to give priority to the input after the last one granted
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val choice = PriorityMux(
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rotateLeft(Vec(io.in.map(_.valid)), lockIdx + UInt(1)),
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rotateLeft(Vec((0 until arbN).map(UInt(_))), lockIdx + UInt(1)))
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val chosen = Mux(locked, lockIdx, choice)
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for (i <- 0 until arbN) {
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io.in(i).ready := io.out.ready && chosen === UInt(i)
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}
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io.out.valid := io.in(chosen).valid
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io.out.bits := io.in(chosen).bits
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when (io.out.fire()) {
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when (!locked) {
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lockIdx := choice
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locked := !io.out.bits.last
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} .elsewhen (io.out.bits.last) {
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locked := Bool(false)
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}
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}
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}
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/** A slave that send decode error for every request it receives */
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class NASTIErrorSlave extends NASTIModule {
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val io = new NASTISlaveIO
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val r_queue = Module(new Queue(UInt(width = nastiRIdBits), 2))
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r_queue.io.enq.valid := io.ar.valid
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r_queue.io.enq.bits := io.ar.bits.id
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io.ar.ready := r_queue.io.enq.ready
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io.r.valid := r_queue.io.deq.valid
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io.r.bits.id := r_queue.io.deq.bits
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io.r.bits.resp := Bits("b11")
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io.r.bits.last := Bool(true)
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r_queue.io.deq.ready := io.r.ready
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val draining = Reg(init = Bool(false))
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io.w.ready := draining
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when (io.aw.fire()) { draining := Bool(true) }
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when (io.w.fire() && io.w.bits.last) { draining := Bool(false) }
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val b_queue = Module(new Queue(UInt(width = nastiWIdBits), 2))
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b_queue.io.enq.valid := io.aw.valid && !draining
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b_queue.io.enq.bits := io.aw.bits.id
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io.aw.ready := b_queue.io.enq.ready && !draining
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io.b.valid := b_queue.io.deq.valid && !draining
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io.b.bits.id := b_queue.io.deq.bits
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io.b.bits.resp := Bits("b11")
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b_queue.io.deq.ready := io.b.ready && !draining
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}
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class NASTIRouter(addrmap: Seq[(BigInt, BigInt)]) extends NASTIModule {
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val nSlaves = addrmap.size
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val io = new Bundle {
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val master = new NASTISlaveIO
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val slave = Vec.fill(nSlaves) { new NASTIMasterIO }
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}
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var ar_ready = Bool(false)
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var aw_ready = Bool(false)
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var w_ready = Bool(false)
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var r_valid_addr = Bool(false)
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var w_valid_addr = Bool(false)
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addrmap.zip(io.slave).zipWithIndex.foreach { case (((base, size), s), i) =>
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val bound = base + size
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require(bigIntPow2(size),
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s"Region size $size is not a power of 2")
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require(base % size == 0,
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f"Region base address $base%x not divisible by $size%d" )
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val ar_addr = io.master.ar.bits.addr
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val ar_match = ar_addr >= UInt(base) && ar_addr < UInt(bound)
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s.ar.valid := io.master.ar.valid && ar_match
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s.ar.bits := io.master.ar.bits
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ar_ready = ar_ready || (s.ar.ready && ar_match)
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r_valid_addr = r_valid_addr || ar_match
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val aw_addr = io.master.aw.bits.addr
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val aw_match = aw_addr >= UInt(base) && aw_addr < UInt(bound)
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s.aw.valid := io.master.aw.valid && aw_match
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s.aw.bits := io.master.aw.bits
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aw_ready = aw_ready || (s.aw.ready && aw_match)
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w_valid_addr = w_valid_addr || aw_match
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val chosen = Reg(init = Bool(false))
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when (s.aw.fire()) { chosen := Bool(true) }
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when (s.w.fire() && s.w.bits.last) { chosen := Bool(false) }
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s.w.valid := io.master.w.valid && chosen
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s.w.bits := io.master.w.bits
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w_ready = w_ready || (s.w.ready && chosen)
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}
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val err_slave = Module(new NASTIErrorSlave)
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err_slave.io.ar.valid := !r_valid_addr && io.master.ar.valid
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err_slave.io.ar.bits := io.master.ar.bits
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err_slave.io.aw.valid := !w_valid_addr && io.master.aw.valid
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err_slave.io.aw.bits := io.master.aw.bits
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err_slave.io.w.valid := io.master.w.valid
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err_slave.io.w.bits := io.master.w.bits
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io.master.ar.ready := ar_ready || (!r_valid_addr && err_slave.io.ar.ready)
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io.master.aw.ready := aw_ready || (!w_valid_addr && err_slave.io.aw.ready)
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io.master.w.ready := w_ready || err_slave.io.w.ready
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val b_arb = Module(new RRArbiter(new NASTIWriteResponseChannel, nSlaves + 1))
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val r_arb = Module(new NASTIReadDataArbiter(nSlaves + 1))
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for (i <- 0 until nSlaves) {
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b_arb.io.in(i) <> io.slave(i).b
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r_arb.io.in(i) <> io.slave(i).r
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}
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b_arb.io.in(nSlaves) <> err_slave.io.b
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r_arb.io.in(nSlaves) <> err_slave.io.r
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io.master.b <> b_arb.io.out
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io.master.r <> r_arb.io.out
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}
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class NASTICrossbar(nMasters: Int, nSlaves: Int, addrmap: Seq[(BigInt, BigInt)])
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extends NASTIModule {
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val io = new Bundle {
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val masters = Vec.fill(nMasters) { new NASTISlaveIO }
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val slaves = Vec.fill(nSlaves) { new NASTIMasterIO }
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}
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val routers = Vec.fill(nMasters) { Module(new NASTIRouter(addrmap)).io }
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val arbiters = Vec.fill(nSlaves) { Module(new NASTIArbiter(nMasters)).io }
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for (i <- 0 until nMasters) {
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routers(i).master <> io.masters(i)
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}
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for (i <- 0 until nSlaves) {
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arbiters(i).master <> Vec(routers.map(r => r.slave(i)))
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io.slaves(i) <> arbiters(i).slave
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}
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}
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case object NASTINMasters extends Field[Int]
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case object NASTINSlaves extends Field[Int]
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object AddrMapTypes {
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type AddrMapEntry = (String, Option[BigInt], MemRegion)
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type AddrMap = Seq[AddrMapEntry]
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}
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import AddrMapTypes._
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abstract class MemRegion { def size: BigInt }
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case class MemSize(size: BigInt) extends MemRegion
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case class MemSubmap(size: BigInt, entries: AddrMap) extends MemRegion
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object Submap {
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def apply(size: BigInt, entries: AddrMapEntry*) =
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new MemSubmap(size, entries)
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}
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case class AddrHashMapEntry(port: Int, start: BigInt, size: BigInt)
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class AddrHashMap(addrmap: AddrMap) {
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val mapping = new HashMap[String, AddrHashMapEntry]
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private def genPairs(addrmap: AddrMap): Seq[(String, AddrHashMapEntry)] = {
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var ind = 0
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var base = BigInt(0)
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var pairs = Seq[(String, AddrHashMapEntry)]()
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addrmap.foreach { case (name, startOpt, region) =>
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region match {
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case MemSize(size) => {
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if (!startOpt.isEmpty) base = startOpt.get
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pairs = (name, AddrHashMapEntry(ind, base, size)) +: pairs
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base += size
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ind += 1
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}
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case MemSubmap(size, submap) => {
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if (!startOpt.isEmpty) base = startOpt.get
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val subpairs = genPairs(submap).map {
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case (subname, AddrHashMapEntry(subind, subbase, subsize)) =>
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(name + ":" + subname,
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AddrHashMapEntry(ind + subind, base + subbase, subsize))
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}
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pairs = subpairs ++ pairs
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ind += subpairs.size
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base += size
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}
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}
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}
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pairs
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}
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for ((name, ind) <- genPairs(addrmap)) { mapping(name) = ind }
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def nEntries: Int = mapping.size
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def apply(name: String): AddrHashMapEntry = mapping(name)
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def get(name: String): Option[AddrHashMapEntry] = mapping.get(name)
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def sortedEntries(): Seq[(String, BigInt, BigInt)] = {
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val arr = new Array[(String, BigInt, BigInt)](mapping.size)
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mapping.foreach { case (name, AddrHashMapEntry(port, base, size)) =>
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arr(port) = (name, base, size)
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}
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arr.toSeq
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}
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}
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case object NASTIAddrMap extends Field[AddrMap]
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case object NASTIAddrHashMap extends Field[AddrHashMap]
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class NASTIInterconnectIO(val nMasters: Int, val nSlaves: Int) extends Bundle {
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/* This is a bit confusing. The interconnect is a slave to the masters and
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* a master to the slaves. Hence why the declarations seem to be backwards. */
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val masters = Vec.fill(nMasters) { new NASTISlaveIO }
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val slaves = Vec.fill(nSlaves) { new NASTIMasterIO }
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override def cloneType =
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new NASTIInterconnectIO(nMasters, nSlaves).asInstanceOf[this.type]
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}
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abstract class NASTIInterconnect extends NASTIModule {
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val nMasters: Int
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val nSlaves: Int
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lazy val io = new NASTIInterconnectIO(nMasters, nSlaves)
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}
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class NASTIRecursiveInterconnect(
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val nMasters: Int, val nSlaves: Int,
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addrmap: AddrMap, base: BigInt = 0) extends NASTIInterconnect {
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private def mapCountSlaves(addrmap: AddrMap): Int = {
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addrmap.map {
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case (_, _, MemSize(_)) => 1
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case (_, _, MemSubmap(_, submap)) => mapCountSlaves(submap)
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}.reduceLeft(_ + _)
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}
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var lastEnd = base
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var slaveInd = 0
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val levelSize = addrmap.size
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val realAddrMap = new ArraySeq[(BigInt, BigInt)](addrmap.size)
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addrmap.zipWithIndex.foreach { case ((_, startOpt, region), i) =>
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val start = startOpt.getOrElse(lastEnd)
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val size = region.size
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realAddrMap(i) = (start, size)
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lastEnd = start + size
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}
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val flatSlaves = if (nMasters > 1) {
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val xbar = Module(new NASTICrossbar(nMasters, levelSize, realAddrMap))
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xbar.io.masters <> io.masters
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xbar.io.slaves
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} else {
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val router = Module(new NASTIRouter(realAddrMap))
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router.io.master <> io.masters.head
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router.io.slave
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}
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addrmap.zip(realAddrMap).zipWithIndex.foreach {
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case (((_, _, region), (start, size)), i) => {
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region match {
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case MemSize(_) =>
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io.slaves(slaveInd) <> flatSlaves(i)
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slaveInd += 1
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case MemSubmap(_, submap) =>
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val subSlaves = mapCountSlaves(submap)
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val ic = Module(new NASTIRecursiveInterconnect(
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1, subSlaves, submap, start))
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ic.io.masters.head <> flatSlaves(i)
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io.slaves.drop(slaveInd).take(subSlaves).zip(ic.io.slaves).foreach {
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case (s, m) => s <> m
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}
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slaveInd += subSlaves
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}
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}
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}
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}
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class NASTITopInterconnect extends NASTIInterconnect {
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val nMasters = params(NASTINMasters)
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val nSlaves = params(NASTINSlaves)
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bigIntPow2(params(MMIOBase))
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val temp = Module(new NASTIRecursiveInterconnect(
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nMasters, nSlaves, params(NASTIAddrMap)))
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temp.io.masters.zip(io.masters).foreach { case (t, i) =>
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t.ar <> i.ar
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t.aw <> i.aw
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// this queue is necessary to break up the aw - w dependence
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// introduced by the TileLink -> NASTI converter
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t.w <> Queue(i.w)
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i.b <> t.b
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i.r <> t.r
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}
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//temp.io.masters <> io.masters
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io.slaves <> temp.io.slaves
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}
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