[groundtest] runs tests with new coreplex and top

src/main/scala/groundtest/Coreplex.scala

@@ -5,6 +5,7 @@ import cde.Parameters
 import diplomacy._
 import coreplex._
 import uncore.devices.NTiles
+import uncore.tilelink2._
 import rocket.TileId
 import uncore.tilelink.TLId
 
@@ -16,6 +17,14 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex
       case TileId => i
     })))
   }
+  tiles.foreach { lm =>
+    l1tol2.node := lm.cachedOut
+    l1tol2.node := lm.uncachedOut
+  }
+
+  val cbusRAM = LazyModule(new TLRAM(AddressSet(0x10000, 0xffff), false, cbus_beatBytes))
+  cbusRAM.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
+
   override lazy val module = new GroundTestCoreplexModule(this, () => new GroundTestCoreplexBundle(this))
 }
 

src/main/scala/groundtest/TestHarness.scala

@@ -1,7 +1,30 @@
 package groundtest
 
 import Chisel._
+import diplomacy._
 import cde.Parameters
+import rocketchip._
+import util._
 
-// !!! TODO: Replace with a groundtest-specific test harness
+class TestHarness(q: Parameters) extends Module {
-class TestHarness(implicit p: Parameters) extends rocketchip.TestHarness(p)
+  val io = new Bundle {
+    val success = Bool(OUTPUT)
+  }
+  implicit val p = q
+
+  val dut = Module(LazyModule(new GroundTestTop(new GroundTestCoreplex()(_))).module)
+  io.success := dut.io.success
+
+  if (dut.io.mem_axi4.nonEmpty) {
+    val memSize = p(ExtMemSize)
+    require(memSize % dut.io.mem_axi4.size == 0)
+    for (axi <- dut.io.mem_axi4.map(_(0))) {
+      val mem = Module(new SimAXIMem(memSize / dut.io.mem_axi4.size))
+      mem.io.axi.ar <> axi.ar
+      mem.io.axi.aw <> axi.aw
+      mem.io.axi.w  <> axi.w
+      axi.r <> LatencyPipe(mem.io.axi.r, p(SimMemLatency))
+      axi.b <> LatencyPipe(mem.io.axi.b, p(SimMemLatency))
+    }
+  }
+}

src/main/scala/groundtest/Tile.scala

@@ -109,7 +109,7 @@ class GroundTestTile(implicit val p: Parameters) extends LazyModule with HasGrou
    val cachedOut = TLOutputNode()
    val uncachedOut = TLOutputNode()
    cachedOut := dcache.node
-   uncachedOut := ucLegacy.node
+   uncachedOut := TLHintHandler()(ucLegacy.node)
    val masterNodes = List(cachedOut, uncachedOut)
 
   lazy val module = new LazyModuleImp(this) {

src/main/scala/groundtest/Top.scala

@@ -0,0 +1,26 @@
+package groundtest
+
+import Chisel._
+import cde.Parameters
+import diplomacy._
+import coreplex._
+import rocketchip._
+
+class GroundTestTop[+C <: GroundTestCoreplex](_coreplex: Parameters => C)(implicit p: Parameters) extends BaseTop(_coreplex)
+    with DirectConnection
+    with PeripheryMasterAXI4Mem
+    with PeripheryTestRAM {
+  override lazy val module = new GroundTestTopModule(this, () => new GroundTestTopBundle(this))
+}
+
+class GroundTestTopBundle[+L <: GroundTestTop[GroundTestCoreplex]](_outer: L) extends BaseTopBundle(_outer)
+    with PeripheryMasterAXI4MemBundle
+    with PeripheryTestRAMBundle {
+  val success = Bool(OUTPUT)
+}
+
+class GroundTestTopModule[+L <: GroundTestTop[GroundTestCoreplex], +B <: GroundTestTopBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io)
+    with PeripheryMasterAXI4MemModule
+    with PeripheryTestRAMModule {
+  io.success := outer.coreplex.module.io.success
+}