riscv/rocket-chip
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[groundtest] runs tests with new coreplex and top

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This commit is contained in:
Henry Cook
2016-11-16 17:05:53 -08:00
parent 24e3216fcf
commit 75d4347192
4 changed files with 61 additions and 3 deletions
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src/main/scala/groundtest/Tile.scala
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@ -109,7 +109,7 @@ class GroundTestTile(implicit val p: Parameters) extends LazyModule with HasGrou
val cachedOut = TLOutputNode()
val uncachedOut = TLOutputNode()
cachedOut := dcache.node
uncachedOut := ucLegacy.node
uncachedOut := TLHintHandler()(ucLegacy.node)
val masterNodes = List(cachedOut, uncachedOut)
lazy val module = new LazyModuleImp(this) {