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util: resynchronize AsyncQueue counters when far side resets

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If the other clock domain is much faster than ours, it's reset
might be shorter than a single cycle in our domain. In that case,
we need to catch the reset and extend it.
This commit is contained in:
Wesley W. Terpstra 2016-10-06 22:31:42 -07:00
parent 5e2609bdd2
commit 75bb94017b
1 changed files with 24 additions and 12 deletions
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32
src/main/scala/util/AsyncQueue.scala
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@ -4,10 +4,10 @@ package util
import Chisel._
object GrayCounter {
def apply(bits: Int, increment: Bool = Bool(true)): UInt = {
def apply(bits: Int, increment: Bool = Bool(true), clear: Bool = Bool(false)): UInt = {
val incremented = Wire(UInt(width=bits))
val binary = AsyncResetReg(incremented, 0)
incremented := binary + increment.asUInt()
val binary = AsyncResetReg(incremented)
incremented := Mux(clear, UInt(0), binary + increment.asUInt())
incremented ^ (incremented >> UInt(1))
}
}
@ -38,18 +38,23 @@ class AsyncQueueSource[T <: Data](gen: T, depth: Int, sync: Int) extends Module
val sink_reset_n = Bool().flip
}
// extend the sink reset to a full cycle (assertion latency <= 1 cycle)
val catch_reset_n = AsyncResetReg(Bool(true), clock, !io.sink_reset_n)
// reset_n has a 1 cycle shorter path to ready than ridx does
val reset_n = AsyncGrayCounter(catch_reset_n.asUInt, sync)(0)
val mem = Reg(Vec(depth, gen)) //This does NOT need to be asynchronously reset.
val widx = GrayCounter(bits+1, io.enq.fire())
val widx = GrayCounter(bits+1, io.enq.fire(), !reset_n)
val ridx = AsyncGrayCounter(io.ridx, sync)
val ready = widx =/= (ridx ^ UInt(depth | depth >> 1))
val index = if (depth == 1) UInt(0) else io.widx(bits-1, 0) ^ (io.widx(bits, bits) << (bits-1))
when (io.enq.fire()) { mem(index) := io.enq.bits }
val ready_reg = AsyncResetReg(ready, 0)
io.enq.ready := ready_reg
val ready_reg = AsyncResetReg(ready.asUInt)(0)
io.enq.ready := ready_reg && reset_n
val widx_reg = AsyncResetReg(widx, 0)
val widx_reg = AsyncResetReg(widx)
io.widx := widx_reg
io.mem := mem
@ -68,7 +73,12 @@ class AsyncQueueSink[T <: Data](gen: T, depth: Int, sync: Int) extends Module {
val source_reset_n = Bool().flip
}
val ridx = GrayCounter(bits+1, io.deq.fire())
// extend the source reset to a full cycle (assertion latency <= 1 cycle)
val catch_reset_n = AsyncResetReg(Bool(true), clock, !io.source_reset_n)
// reset_n has a 1 cycle shorter path to valid than widx does
val reset_n = AsyncGrayCounter(catch_reset_n.asUInt, sync)(0)
val ridx = GrayCounter(bits+1, io.deq.fire(), !reset_n)
val widx = AsyncGrayCounter(io.widx, sync)
val valid = ridx =/= widx
@ -81,9 +91,11 @@ class AsyncQueueSink[T <: Data](gen: T, depth: Int, sync: Int) extends Module {
// be considered unless the asynchronously reset deq valid register is set.
io.deq.bits := RegEnable(io.mem(index), valid)
io.deq.valid := AsyncResetReg(valid, 0)
val valid_reg = AsyncResetReg(valid.asUInt)(0)
io.deq.valid := valid_reg && reset_n
io.ridx := AsyncResetReg(ridx, 0)
val ridx_reg = AsyncResetReg(ridx)
io.ridx := ridx_reg
}
class AsyncQueue[T <: Data](gen: T, depth: Int = 8, sync: Int = 3) extends Crossing[T] {