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tilelink2: expand data correctly in D channel narrower

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This commit is contained in:
Wesley W. Terpstra 2016-09-04 19:48:21 -07:00
parent 0faa8c4051
commit 757d46279e
1 changed files with 10 additions and 5 deletions
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15
src/main/scala/uncore/tilelink2/Narrower.scala
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@ -4,6 +4,7 @@ package uncore.tilelink2
import Chisel._ import Chisel._
import chisel3.internal.sourceinfo.SourceInfo import chisel3.internal.sourceinfo.SourceInfo
import scala.math.{min,max}
// innBeatBytes => the bus width after the adapter // innBeatBytes => the bus width after the adapter
class TLNarrower(innerBeatBytes: Int) extends LazyModule class TLNarrower(innerBeatBytes: Int) extends LazyModule
@ -62,10 +63,6 @@ class TLNarrower(innerBeatBytes: Int) extends LazyModule
val first = count === UInt(0) val first = count === UInt(0)
val limit = UIntToOH1(in.size(), log2Ceil(innerBeatBytes)) >> log2Ceil(outerBeatBytes) val limit = UIntToOH1(in.size(), log2Ceil(innerBeatBytes)) >> log2Ceil(outerBeatBytes)
val last = count === limit || !edge.hasData(in) val last = count === limit || !edge.hasData(in)
val cases = Vec.tabulate (log2Ceil(ratio)+1) { i =>
val pow = 1 << i
Fill(1 << (ratio-i), data((pow+1)*outerBeatBytes*8-1, pow*outerBeatBytes*8))
}
when (fire) { when (fire) {
rdata := data rdata := data
@ -73,10 +70,18 @@ class TLNarrower(innerBeatBytes: Int) extends LazyModule
when (last) { count := UInt(0) } when (last) { count := UInt(0) }
} }
val cases = Seq.tabulate(log2Ceil(ratio)+1) { i =>
val pow = 1 << i
Fill(1 << (log2Ceil(ratio)-i), data(pow*outerBeatBytes*8-1, 0))
}
val mux = Vec.tabulate(log2Ceil(edge.maxTransfer)+1) { lgSize =>
cases(min(max(lgSize - log2Ceil(outerBeatBytes), 0), log2Ceil(ratio)))
}
if (edge.staticHasData(in) == Some(false)) { if (edge.staticHasData(in) == Some(false)) {
(Bool(true), UInt(0)) (Bool(true), UInt(0))
} else { } else {
(last, Mux1H(limit, cases)) (last, mux(in.size()))
} }
} }