Removed broken or unfinished modules, new MemPipeIO converter

uncore/src/main/scala/bigmem.scala

@@ -0,0 +1,80 @@
+// See LICENSE for license details.
+
+package uncore
+import Chisel._
+
+class BigMem[T <: Data](n: Int, preLatency: Int, postLatency: Int, leaf: Mem[UInt], noMask: Boolean = false)(gen: => T) extends Module
+{
+  class Inputs extends Bundle {
+    val addr = UInt(INPUT, log2Up(n))
+    val rw = Bool(INPUT)
+    val wdata = gen.asInput
+    val wmask = gen.asInput
+    override def clone = new Inputs().asInstanceOf[this.type]
+  }
+  val io = new Bundle {
+    val in = Valid(new Inputs).flip
+    val rdata = gen.asOutput
+  }
+  val data = gen
+  val colMux = if (2*data.getWidth <= leaf.data.getWidth && n > leaf.n) 1 << math.floor(math.log(leaf.data.getWidth/data.getWidth)/math.log(2)).toInt else 1
+  val nWide = if (data.getWidth > leaf.data.getWidth) 1+(data.getWidth-1)/leaf.data.getWidth else 1
+  val nDeep = if (n > colMux*leaf.n) 1+(n-1)/(colMux*leaf.n) else 1
+  if (nDeep > 1 || colMux > 1)
+    require(isPow2(n) && isPow2(leaf.n))
+
+  val rdataDeep = Vec.fill(nDeep){Bits()}
+  val rdataSel = Vec.fill(nDeep){Bool()}
+  for (i <- 0 until nDeep) {
+    val in = Pipe(io.in.valid && (if (nDeep == 1) Bool(true) else UInt(i) === io.in.bits.addr(log2Up(n)-1, log2Up(n/nDeep))), io.in.bits, preLatency)
+    val idx = in.bits.addr(log2Up(n/nDeep/colMux)-1, 0)
+    val wdata = in.bits.wdata.toBits
+    val wmask = in.bits.wmask.toBits
+    val ren = in.valid && !in.bits.rw
+    val reg_ren = Reg(next=ren)
+    val rdata = Vec.fill(nWide){Bits()}
+
+    val r = Pipe(ren, in.bits.addr, postLatency)
+
+    for (j <- 0 until nWide) {
+      val mem = leaf.clone
+      var dout: Bits = null
+      val ridx = if (postLatency > 0) Reg(Bits()) else null
+
+      var wmask0 = Fill(colMux, wmask(math.min(wmask.getWidth, leaf.data.getWidth*(j+1))-1, leaf.data.getWidth*j))
+      if (colMux > 1)
+        wmask0 = wmask0 & FillInterleaved(gen.getWidth, UIntToOH(in.bits.addr(log2Up(n/nDeep)-1, log2Up(n/nDeep/colMux)), log2Up(colMux)))
+      val wdata0 = Fill(colMux, wdata(math.min(wdata.getWidth, leaf.data.getWidth*(j+1))-1, leaf.data.getWidth*j))
+      when (in.valid) {
+        when (in.bits.rw) {
+          if (noMask)
+            mem.write(idx, wdata0)
+          else
+            mem.write(idx, wdata0, wmask0)
+        }
+        .otherwise { if (postLatency > 0) ridx := idx }
+      }
+
+      if (postLatency == 0) {
+        dout = mem(idx)
+      } else if (postLatency == 1) {
+        dout = mem(ridx)
+      } else
+        dout = Pipe(reg_ren, mem(ridx), postLatency-1).bits
+
+      rdata(j) := dout
+    }
+    val rdataWide = rdata.reduceLeft((x, y) => Cat(y, x))
+
+    var colMuxOut = rdataWide
+    if (colMux > 1) {
+      val colMuxIn = Vec((0 until colMux).map(k => rdataWide(gen.getWidth*(k+1)-1, gen.getWidth*k)))
+      colMuxOut = colMuxIn(r.bits(log2Up(n/nDeep)-1, log2Up(n/nDeep/colMux)))
+    }
+
+    rdataDeep(i) := colMuxOut
+    rdataSel(i) := r.valid
+  }
+
+  io.rdata := Mux1H(rdataSel, rdataDeep)
+}

uncore/src/main/scala/cache.scala

@@ -96,502 +96,3 @@ class MetadataArray[T <: Metadata](makeRstVal: () => T) extends CacheModule {
   io.read.ready := !rst && !io.write.valid // so really this could be a 6T RAM
   io.write.ready := !rst
 }
-
-abstract trait L2HellaCacheParameters extends CacheParameters 
-  with CoherenceAgentParameters
-
-abstract class L2HellaCacheBundle extends Bundle with L2HellaCacheParameters
-abstract class L2HellaCacheModule extends Module with L2HellaCacheParameters
-
-trait HasL2Id extends Bundle with CoherenceAgentParameters {
-  val id = UInt(width  = log2Up(nTransactors))
-}
-
-trait HasL2InternalRequestState extends L2HellaCacheBundle {
-  val tag_match = Bool()
-  val meta = new L2Metadata
-  val way_en = Bits(width = nWays)
-}
-
-object L2Metadata {
-  def apply(tag: Bits, coh: MasterMetadata) = {
-    val meta = new L2Metadata
-    meta.tag := tag
-    meta.coh := coh
-    meta
-  }
-}
-class L2Metadata extends Metadata with L2HellaCacheParameters {
-  val coh = co.masterMetadataOnFlush.clone
-}
-
-class L2MetaReadReq extends MetaReadReq with HasL2Id {
-  val tag = Bits(width = tagBits)
-}
-
-class L2MetaWriteReq extends MetaWriteReq[L2Metadata](new L2Metadata)
-  with HasL2Id
-
-class L2MetaResp extends L2HellaCacheBundle
-  with HasL2Id 
-  with HasL2InternalRequestState
-
-class L2MetadataArray extends L2HellaCacheModule {
-  val io = new Bundle {
-    val read = Decoupled(new L2MetaReadReq).flip
-    val write = Decoupled(new L2MetaWriteReq).flip
-    val resp = Valid(new L2MetaResp)
-  }
-
-  val meta = Module(new MetadataArray(() => L2Metadata(UInt(0), co.masterMetadataOnFlush)))
-  meta.io.read <> io.read
-  meta.io.write <> io.write
-  
-  val s1_clk_en = Reg(next = io.read.fire())
-  val s1_tag = RegEnable(io.read.bits.tag, io.read.valid)
-  val s1_id = RegEnable(io.read.bits.id, io.read.valid)
-  def wayMap[T <: Data](f: Int => T) = Vec((0 until nWays).map(f))
-  val s1_tag_eq_way = wayMap((w: Int) => meta.io.resp(w).tag === s1_tag)
-  val s1_tag_match_way = wayMap((w: Int) => s1_tag_eq_way(w) && co.isValid(meta.io.resp(w).coh)).toBits
-  val s2_tag_match_way = RegEnable(s1_tag_match_way, s1_clk_en)
-  val s2_tag_match = s2_tag_match_way.orR
-  val s2_hit_coh = Mux1H(s2_tag_match_way, wayMap((w: Int) => RegEnable(meta.io.resp(w).coh, s1_clk_en)))
-  //val s2_hit = s2_tag_match && tl.co.isHit(s2_req.cmd, s2_hit_state) && s2_hit_state === tl.co.newStateOnHit(s2_req.cmd, s2_hit_state)
-
-  val replacer = params(Replacer)()
-  val s1_replaced_way_en = UIntToOH(replacer.way)
-  val s2_replaced_way_en = UIntToOH(RegEnable(replacer.way, s1_clk_en))
-  val s2_repl_meta = Mux1H(s2_replaced_way_en, wayMap((w: Int) => 
-    RegEnable(meta.io.resp(w), s1_clk_en && s1_replaced_way_en(w))).toSeq)
-
-  io.resp.valid := Reg(next = s1_clk_en)
-  io.resp.bits.id := RegEnable(s1_id, s1_clk_en)
-  io.resp.bits.tag_match := s2_tag_match
-  io.resp.bits.meta := Mux(s2_tag_match, 
-    L2Metadata(s2_repl_meta.tag, s2_hit_coh), 
-    s2_repl_meta)
-  io.resp.bits.way_en := Mux(s2_tag_match, s2_tag_match_way, s2_replaced_way_en)
-}
-
-class L2DataReadReq extends L2HellaCacheBundle with HasL2Id {
-  val way_en = Bits(width = nWays)
-  val addr   = Bits(width = params(TLAddrBits))
-}
-
-class L2DataWriteReq extends L2DataReadReq {
-  val wmask  = Bits(width = params(TLWriteMaskBits))
-  val data   = Bits(width = params(TLDataBits))
-}
-
-class L2DataResp extends Bundle with HasL2Id {
-  val data   = Bits(width = params(TLDataBits))
-}
-
-class L2DataArray extends L2HellaCacheModule {
-  val io = new Bundle {
-    val read = Decoupled(new L2DataReadReq).flip
-    val write = Decoupled(new L2DataWriteReq).flip
-    val resp = Valid(new L2DataResp)
-  }
-
-  val waddr = io.write.bits.addr
-  val raddr = io.read.bits.addr
-  val wmask = FillInterleaved(wordBits, io.write.bits.wmask)
-  val resp = (0 until nWays).map { w =>
-    val array = Mem(Bits(width=params(RowBits)), nSets*refillCycles, seqRead = true)
-    when (io.write.bits.way_en(w) && io.write.valid) {
-      array.write(waddr, io.write.bits.data, wmask)
-    }
-    array(RegEnable(raddr, io.read.bits.way_en(w) && io.read.valid))
-  }
-  io.resp.valid := ShiftRegister(io.read.valid, 2)
-  io.resp.bits.id := ShiftRegister(io.read.bits.id, 2)
-  io.resp.bits.data := Mux1H(ShiftRegister(io.read.bits.way_en, 2), resp)
-
-  io.read.ready := Bool(true)
-  io.write.ready := Bool(true)
-}
-
-class L2HellaCache(bankId: Int, innerId: String, outerId: String) extends 
-    CoherenceAgent(innerId, outerId) with L2HellaCacheParameters {
-
-  require(isPow2(nSets))
-  require(isPow2(nWays)) 
-  require(refillCycles == 1)
-
-  val tshrfile = Module(new TSHRFile(bankId, innerId, outerId))
-  val meta = Module(new L2MetadataArray)
-  val data = Module(new L2DataArray)
-
-  tshrfile.io.inner <> io.inner
-  tshrfile.io.meta_read <> meta.io.read
-  tshrfile.io.meta_write <> meta.io.write
-  tshrfile.io.meta_resp <> meta.io.resp
-  tshrfile.io.data_read <> data.io.read
-  tshrfile.io.data_write <> data.io.write
-  tshrfile.io.data_resp <> data.io.resp
-  io.outer <> tshrfile.io.outer
-  io.incoherent <> tshrfile.io.incoherent
-}
-
-
-class TSHRFile(bankId: Int, innerId: String, outerId: String) extends L2HellaCacheModule {
-  val io = new Bundle {
-    val inner = Bundle(new TileLinkIO, {case TLId => innerId}).flip
-    val outer = Bundle(new UncachedTileLinkIO, {case TLId => outerId})
-    val incoherent = Vec.fill(nClients){Bool()}.asInput
-    val meta_read = Decoupled(new L2MetaReadReq)
-    val meta_write = Decoupled(new L2MetaWriteReq)
-    val meta_resp = Valid(new L2MetaResp).flip
-    val data_read = Decoupled(new L2DataReadReq)
-    val data_write = Decoupled(new L2DataWriteReq)
-    val data_resp = Valid(new L2DataResp).flip
-  }
-
-  // Wiring helper funcs
-  def doOutputArbitration[T <: Data](out: DecoupledIO[T], ins: Seq[DecoupledIO[T]]) {
-    val arb = Module(new RRArbiter(out.bits.clone, ins.size))
-    out <> arb.io.out
-    arb.io.in zip ins map { case (a, in) => a <> in }
-  }
-
-  def doInputRouting[T <: HasL2Id](in: ValidIO[T], outs: Seq[ValidIO[T]]) {
-    outs.map(_.bits := in.bits)
-    outs.zipWithIndex.map { case (o, i) => o.valid := UInt(i) === in.bits.id }
-  }
-
-  // Create TSHRs for outstanding transactions
-  val trackerList = (0 until nReleaseTransactors).map { id => 
-    Module(new L2VoluntaryReleaseTracker(id, bankId, innerId, outerId)) 
-  } ++ (nReleaseTransactors until nTransactors).map { id => 
-    Module(new L2AcquireTracker(id, bankId, innerId, outerId))
-  }
-  
-  // Propagate incoherence flags
-  trackerList.map(_.io.tile_incoherent := io.incoherent.toBits)
-
-  // Handle acquire transaction initiation
-  val acquire = io.inner.acquire
-  val any_acquire_conflict = trackerList.map(_.io.has_acquire_conflict).reduce(_||_)
-  val block_acquires = any_acquire_conflict
-
-  val alloc_arb = Module(new Arbiter(Bool(), trackerList.size))
-  for( i <- 0 until trackerList.size ) {
-    val t = trackerList(i).io.inner
-    alloc_arb.io.in(i).valid := t.acquire.ready
-    t.acquire.bits := acquire.bits
-    t.acquire.valid := alloc_arb.io.in(i).ready
-  }
-  acquire.ready := trackerList.map(_.io.inner.acquire.ready).reduce(_||_) && !block_acquires
-  alloc_arb.io.out.ready := acquire.valid && !block_acquires
-
-  // Handle probe requests
-  doOutputArbitration(io.inner.probe, trackerList.map(_.io.inner.probe))
-
-  // Handle releases, which might be voluntary and might have data
-  val release = io.inner.release
-  val voluntary = co.isVoluntary(release.bits.payload)
-  val any_release_conflict = trackerList.tail.map(_.io.has_release_conflict).reduce(_||_)
-  val block_releases = Bool(false)
-  val conflict_idx = Vec(trackerList.map(_.io.has_release_conflict)).lastIndexWhere{b: Bool => b}
-  //val release_idx = Mux(voluntary, Mux(any_release_conflict, conflict_idx, UInt(0)), release.bits.payload.master_xact_id) // TODO: Add merging logic to allow allocated AcquireTracker to handle conflicts, send all necessary grants, use first sufficient response
-  val release_idx = Mux(voluntary, UInt(0), release.bits.payload.master_xact_id)
-  for( i <- 0 until trackerList.size ) {
-    val t = trackerList(i).io.inner
-    t.release.bits := release.bits 
-    t.release.valid := release.valid && (release_idx === UInt(i)) && !block_releases
-  }
-  release.ready := Vec(trackerList.map(_.io.inner.release.ready)).read(release_idx) && !block_releases
-
-  // Reply to initial requestor
-  doOutputArbitration(io.inner.grant, trackerList.map(_.io.inner.grant))
-
-  // Free finished transactions
-  val ack = io.inner.finish
-  trackerList.map(_.io.inner.finish.valid := ack.valid)
-  trackerList.map(_.io.inner.finish.bits := ack.bits)
-  ack.ready := Bool(true)
-
-  // Arbitrate for the outer memory port
-  val outer_arb = Module(new UncachedTileLinkIOArbiterThatPassesId(trackerList.size),
-                         {case TLId => outerId})
-  outer_arb.io.in zip  trackerList map { case(arb, t) => arb <> t.io.outer }
-  io.outer <> outer_arb.io.out
-
-  // Local memory
-  doOutputArbitration(io.meta_read, trackerList.map(_.io.meta_read))
-  doOutputArbitration(io.meta_write, trackerList.map(_.io.meta_write))
-  doOutputArbitration(io.data_read, trackerList.map(_.io.data_read))
-  doOutputArbitration(io.data_write, trackerList.map(_.io.data_write))
-  doInputRouting(io.meta_resp, trackerList.map(_.io.meta_resp))
-  doInputRouting(io.data_resp, trackerList.map(_.io.data_resp))
-
-}
-
-
-abstract class L2XactTracker(innerId: String, outerId: String) extends L2HellaCacheModule {
-  val io = new Bundle {
-    val inner = Bundle(new TileLinkIO, {case TLId => innerId}).flip
-    val outer = Bundle(new UncachedTileLinkIO, {case TLId => outerId})
-    val tile_incoherent = Bits(INPUT, nClients)
-    val has_acquire_conflict = Bool(OUTPUT)
-    val has_release_conflict = Bool(OUTPUT)
-    val meta_read = Decoupled(new L2MetaReadReq)
-    val meta_write = Decoupled(new L2MetaWriteReq)
-    val meta_resp = Valid(new L2MetaResp).flip
-    val data_read = Decoupled(new L2DataReadReq)
-    val data_write = Decoupled(new L2DataWriteReq)
-    val data_resp = Valid(new L2DataResp).flip
-  }
-
-  val c_acq = io.inner.acquire.bits
-  val c_rel = io.inner.release.bits
-  val c_gnt = io.inner.grant.bits
-  val c_ack = io.inner.finish.bits
-  val m_gnt = io.outer.grant.bits
-
-}
-
-class L2VoluntaryReleaseTracker(trackerId: Int, bankId: Int, innerId: String, outerId: String) extends L2XactTracker(innerId, outerId) {
-  val s_idle :: s_mem :: s_ack :: s_busy :: Nil = Enum(UInt(), 4)
-  val state = Reg(init=s_idle)
-  val xact  = Reg{ new Release }
-  val xact_internal = Reg{ new L2MetaResp }
-  val init_client_id = Reg(init=UInt(0, width = log2Up(nClients)))
-
-  io.has_acquire_conflict := Bool(false)
-  io.has_release_conflict := co.isCoherenceConflict(xact.addr, c_rel.payload.addr) && 
-                               (state != s_idle)
-
-  io.outer.grant.ready := Bool(false)
-  io.outer.acquire.valid := Bool(false)
-  io.outer.acquire.bits.header.src := UInt(bankId) 
-  io.outer.acquire.bits.payload := Bundle(Acquire(co.getUncachedWriteAcquireType,
-                                            xact.addr,
-                                            UInt(trackerId),
-                                            xact.data),
-                                    { case TLId => outerId })
-  io.inner.acquire.ready := Bool(false)
-  io.inner.probe.valid := Bool(false)
-  io.inner.release.ready := Bool(false)
-  io.inner.grant.valid := Bool(false)
-  io.inner.grant.bits.header.src := UInt(bankId)
-  io.inner.grant.bits.header.dst := init_client_id
-  io.inner.grant.bits.payload := Grant(co.getGrantType(xact, co.masterMetadataOnFlush),// TODO xact_internal.meta)
-                                        xact.client_xact_id,
-                                        UInt(trackerId))
-
-  io.data_read.valid := Bool(false)
-  io.data_write.valid := Bool(false)
-  io.data_write.bits.id := UInt(trackerId)
-  io.data_write.bits.way_en := xact_internal.way_en
-  io.data_write.bits.addr := xact.addr
-  io.data_write.bits.wmask := SInt(-1)
-  io.data_write.bits.data := xact.data
-  io.meta_read.valid := Bool(false)
-  io.meta_read.bits.id := UInt(trackerId)
-  io.meta_read.bits.idx := xact.addr(untagBits-1,blockOffBits)
-  io.meta_read.bits.tag := xact.addr >> UInt(untagBits)
-  io.meta_write.valid := Bool(false)
-  io.meta_write.bits.id := UInt(trackerId)
-  io.meta_write.bits.idx := xact.addr(untagBits-1,blockOffBits)
-  io.meta_write.bits.way_en := xact_internal.way_en
-  io.meta_write.bits.data := xact_internal.meta
-
-  when(io.meta_resp.valid) { xact_internal := io.meta_resp.bits }
-
-  switch (state) {
-    is(s_idle) {
-      io.inner.release.ready := Bool(true)
-      when( io.inner.release.valid ) {
-        xact := c_rel.payload
-        init_client_id := c_rel.header.src
-        state := s_mem
-      }
-    }/*
-    is(s_meta_read) {
-      when(io.meta_read.ready) state := s_meta_resp
-    }
-    is(s_meta_resp) {
-      when(io.meta_resp.valid) {
-        xact_internal.meta := tl.co.masterMetadataOnRelease(xact, xact_internal.meta, init_client_id))
-        state := Mux(s_meta_write
-          Mux(co.messageHasData(xact), s_mem, s_ack)
-    }*/
-    is(s_mem) {
-      io.outer.acquire.valid := Bool(true)
-      when(io.outer.acquire.ready) { state := s_ack }
-    }
-    is(s_ack) {
-      io.inner.grant.valid := Bool(true)
-      when(io.inner.grant.ready) { state := s_idle }
-    }
-  }
-}
-
-class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: String) extends L2XactTracker(innerId, outerId) {
-  val s_idle :: s_probe :: s_mem_read :: s_mem_write :: s_make_grant :: s_busy :: Nil = Enum(UInt(), 6)
-  val state = Reg(init=s_idle)
-  val xact  = Reg{ new Acquire }
-  val xact_internal = Reg{ new L2MetaResp }
-  val init_client_id = Reg(init=UInt(0, width = log2Up(nClients)))
-  //TODO: Will need id reg for merged release xacts
-  
-  val release_count = if (nClients == 1) UInt(0) else Reg(init=UInt(0, width = log2Up(nClients)))
-  val probe_flags = Reg(init=Bits(0, width = nClients))
-  val curr_p_id = PriorityEncoder(probe_flags)
-
-  val pending_outer_write = co.messageHasData(xact)
-  val pending_outer_read = co.requiresOuterRead(xact.a_type)
-  val outer_write_acq = Bundle(Acquire(co.getUncachedWriteAcquireType, 
-                                       xact.addr, UInt(trackerId), xact.data),
-                                    { case TLId => outerId })
-  val outer_write_rel = Bundle(Acquire(co.getUncachedWriteAcquireType, 
-                                       xact.addr, UInt(trackerId), c_rel.payload.data),
-                                    { case TLId => outerId })
-  val outer_read = Bundle(Acquire(co.getUncachedReadAcquireType, xact.addr, UInt(trackerId)),
-                                    { case TLId => outerId })
-
-  val probe_initial_flags = Bits(width = nClients)
-  probe_initial_flags := Bits(0)
-  if (nClients > 1) {
-    // issue self-probes for uncached read xacts to facilitate I$ coherence
-    val probe_self = Bool(true) //co.needsSelfProbe(io.inner.acquire.bits.payload)
-    val myflag = Mux(probe_self, Bits(0), UIntToOH(c_acq.header.src(log2Up(nClients)-1,0)))
-    probe_initial_flags := ~(io.tile_incoherent | myflag)
-  }
-
-  io.has_acquire_conflict := co.isCoherenceConflict(xact.addr, c_acq.payload.addr) && (state != s_idle)
-  io.has_release_conflict := co.isCoherenceConflict(xact.addr, c_rel.payload.addr) && (state != s_idle)
-
-  io.outer.acquire.valid := Bool(false)
-  io.outer.acquire.bits.header.src := UInt(bankId)
-  io.outer.acquire.bits.payload := outer_read 
-  io.outer.grant.ready := io.inner.grant.ready
-
-  io.inner.probe.valid := Bool(false)
-  io.inner.probe.bits.header.src := UInt(bankId)
-  io.inner.probe.bits.header.dst := curr_p_id
-  io.inner.probe.bits.payload := Probe(co.getProbeType(xact, /*xact_internal.meta), TODO*/
-                                          co.masterMetadataOnFlush),
-                                        xact.addr,
-                                        UInt(trackerId))
-
-  val grant_type = co.getGrantType(xact, co.masterMetadataOnFlush)// TODO xact_internal.meta)
-  io.inner.grant.valid := Bool(false)
-  io.inner.grant.bits.header.src := UInt(bankId)
-  io.inner.grant.bits.header.dst := init_client_id
-  io.inner.grant.bits.payload := Grant(grant_type,
-                                        xact.client_xact_id,
-                                        UInt(trackerId),
-                                        m_gnt.payload.data)
-
-  io.inner.acquire.ready := Bool(false)
-  io.inner.release.ready := Bool(false)
-
-  io.data_read.valid := Bool(false)
-  io.data_read.bits.id := UInt(trackerId)
-  io.data_read.bits.way_en := xact_internal.way_en
-  io.data_read.bits.addr := xact.addr 
-  io.data_write.valid := Bool(false)
-  io.data_write.bits.id := UInt(trackerId)
-  io.data_write.bits.way_en := xact_internal.way_en
-  io.data_write.bits.addr := xact.addr
-  io.data_write.bits.wmask := SInt(-1)
-  io.data_write.bits.data := xact.data
-  io.meta_read.valid := Bool(false)
-  io.meta_read.bits.id := UInt(trackerId)
-  io.meta_read.bits.idx := xact.addr(untagBits-1,blockOffBits)
-  io.meta_read.bits.tag := xact.addr >> UInt(untagBits)
-  io.meta_write.valid := Bool(false)
-  io.meta_write.bits.id := UInt(trackerId)
-  io.meta_write.bits.idx := xact.addr(untagBits-1,blockOffBits)
-  io.meta_write.bits.way_en := xact_internal.way_en
-  io.meta_write.bits.data := xact_internal.meta
-
-  when(io.meta_resp.valid && io.meta_resp.bits.id === UInt(trackerId)) { xact_internal := io.meta_resp.bits }
-
-  switch (state) {
-    is(s_idle) {
-      io.inner.acquire.ready := Bool(true)
-      val needs_outer_write = co.messageHasData(c_acq.payload)
-      val needs_outer_read = co.requiresOuterRead(c_acq.payload.a_type)
-      when( io.inner.acquire.valid ) {
-        xact := c_acq.payload
-        init_client_id := c_acq.header.src
-        probe_flags := probe_initial_flags
-        if(nClients > 1) {
-          release_count := PopCount(probe_initial_flags)
-          state := Mux(probe_initial_flags.orR, s_probe,
-                    Mux(needs_outer_write, s_mem_write,
-                      Mux(needs_outer_read, s_mem_read, s_make_grant)))
-        } else state := Mux(needs_outer_write, s_mem_write,
-                        Mux(needs_outer_read, s_mem_read, s_make_grant))
-      }
-    }
-    // s_read_meta 
-    // xact_internal := resp
-    is(s_probe) {
-      // Generate probes
-      io.inner.probe.valid := probe_flags.orR
-      when(io.inner.probe.ready) {
-        probe_flags := probe_flags & ~(UIntToOH(curr_p_id))
-      }
-
-      // Handle releases, which may have data to be written back
-      when(io.inner.release.valid) {
-        //xact_internal.meta.coh := tl.co.masterMetadataOnRelease(
-        //                        io.inner.release.bits.payload, 
-        //                        xact_internal.meta.coh,
-        //                        init_client_id)
-        when(co.messageHasData(c_rel.payload)) {
-          io.outer.acquire.valid := Bool(true)
-          io.outer.acquire.bits.payload := outer_write_rel
-          when(io.outer.acquire.ready) {
-            io.inner.release.ready := Bool(true)
-            if(nClients > 1) release_count := release_count - UInt(1)
-            when(release_count === UInt(1)) {
-              state := Mux(pending_outer_write, s_mem_write,
-                        Mux(pending_outer_read, s_mem_read, s_make_grant))
-            }
-          }
-        } .otherwise {
-          io.inner.release.ready := Bool(true)
-          if(nClients > 1) release_count := release_count - UInt(1)
-          when(release_count === UInt(1)) {
-            state := Mux(pending_outer_write, s_mem_write, 
-                      Mux(pending_outer_read, s_mem_read, s_make_grant))
-          }
-        }
-      }
-    }
-    is(s_mem_read) {
-      io.outer.acquire.valid := Bool(true)
-      io.outer.acquire.bits.payload := outer_read
-      when(io.outer.acquire.ready) {
-        state := Mux(co.requiresAckForGrant(grant_type), s_busy, s_idle)
-      }
-    }
-    is(s_mem_write) {
-      io.outer.acquire.valid := Bool(true)
-      io.outer.acquire.bits.payload := outer_write_acq
-      when(io.outer.acquire.ready) { 
-        state := Mux(pending_outer_read, s_mem_read, s_make_grant)
-      }
-    }
-    is(s_make_grant) {
-      io.inner.grant.valid := Bool(true)
-      when(io.inner.grant.ready) { 
-        state := Mux(co.requiresAckForGrant(grant_type), s_busy, s_idle)
-      }
-    }
-    is(s_busy) { // Nothing left to do but wait for transaction to complete
-      when(io.outer.grant.valid && m_gnt.payload.client_xact_id === UInt(trackerId)) {
-        io.inner.grant.valid := Bool(true)
-      }
-      when(io.inner.finish.valid && c_ack.payload.master_xact_id === UInt(trackerId)) {
-        state := s_idle
-      }
-    }
-  }
-}

uncore/src/main/scala/llc.scala

@@ -1,554 +0,0 @@
-// See LICENSE for license details.
-
-package uncore
-import Chisel._
-
-class BigMem[T <: Data](n: Int, preLatency: Int, postLatency: Int, leaf: Mem[UInt], noMask: Boolean = false)(gen: => T) extends Module
-{
-  class Inputs extends Bundle {
-    val addr = UInt(INPUT, log2Up(n))
-    val rw = Bool(INPUT)
-    val wdata = gen.asInput
-    val wmask = gen.asInput
-    override def clone = new Inputs().asInstanceOf[this.type]
-  }
-  val io = new Bundle {
-    val in = Valid(new Inputs).flip
-    val rdata = gen.asOutput
-  }
-  val data = gen
-  val colMux = if (2*data.getWidth <= leaf.data.getWidth && n > leaf.n) 1 << math.floor(math.log(leaf.data.getWidth/data.getWidth)/math.log(2)).toInt else 1
-  val nWide = if (data.getWidth > leaf.data.getWidth) 1+(data.getWidth-1)/leaf.data.getWidth else 1
-  val nDeep = if (n > colMux*leaf.n) 1+(n-1)/(colMux*leaf.n) else 1
-  if (nDeep > 1 || colMux > 1)
-    require(isPow2(n) && isPow2(leaf.n))
-
-  val rdataDeep = Vec.fill(nDeep){Bits()}
-  val rdataSel = Vec.fill(nDeep){Bool()}
-  for (i <- 0 until nDeep) {
-    val in = Pipe(io.in.valid && (if (nDeep == 1) Bool(true) else UInt(i) === io.in.bits.addr(log2Up(n)-1, log2Up(n/nDeep))), io.in.bits, preLatency)
-    val idx = in.bits.addr(log2Up(n/nDeep/colMux)-1, 0)
-    val wdata = in.bits.wdata.toBits
-    val wmask = in.bits.wmask.toBits
-    val ren = in.valid && !in.bits.rw
-    val reg_ren = Reg(next=ren)
-    val rdata = Vec.fill(nWide){Bits()}
-
-    val r = Pipe(ren, in.bits.addr, postLatency)
-
-    for (j <- 0 until nWide) {
-      val mem = leaf.clone
-      var dout: Bits = null
-      val ridx = if (postLatency > 0) Reg(Bits()) else null
-
-      var wmask0 = Fill(colMux, wmask(math.min(wmask.getWidth, leaf.data.getWidth*(j+1))-1, leaf.data.getWidth*j))
-      if (colMux > 1)
-        wmask0 = wmask0 & FillInterleaved(gen.getWidth, UIntToOH(in.bits.addr(log2Up(n/nDeep)-1, log2Up(n/nDeep/colMux)), log2Up(colMux)))
-      val wdata0 = Fill(colMux, wdata(math.min(wdata.getWidth, leaf.data.getWidth*(j+1))-1, leaf.data.getWidth*j))
-      when (in.valid) {
-        when (in.bits.rw) {
-          if (noMask)
-            mem.write(idx, wdata0)
-          else
-            mem.write(idx, wdata0, wmask0)
-        }
-        .otherwise { if (postLatency > 0) ridx := idx }
-      }
-
-      if (postLatency == 0) {
-        dout = mem(idx)
-      } else if (postLatency == 1) {
-        dout = mem(ridx)
-      } else
-        dout = Pipe(reg_ren, mem(ridx), postLatency-1).bits
-
-      rdata(j) := dout
-    }
-    val rdataWide = rdata.reduceLeft((x, y) => Cat(y, x))
-
-    var colMuxOut = rdataWide
-    if (colMux > 1) {
-      val colMuxIn = Vec((0 until colMux).map(k => rdataWide(gen.getWidth*(k+1)-1, gen.getWidth*k)))
-      colMuxOut = colMuxIn(r.bits(log2Up(n/nDeep)-1, log2Up(n/nDeep/colMux)))
-    }
-
-    rdataDeep(i) := colMuxOut
-    rdataSel(i) := r.valid
-  }
-
-  io.rdata := Mux1H(rdataSel, rdataDeep)
-}
-
-class LLCDataReq(ways: Int) extends MemReqCmd
-{
-  val way = UInt(width = log2Up(ways))
-  val isWriteback = Bool()
-  override def clone = new LLCDataReq(ways).asInstanceOf[this.type]
-}
-
-class LLCTagReq(ways: Int) extends HasMemAddr
-{
-  val way = UInt(width = log2Up(ways))
-  override def clone = new LLCTagReq(ways).asInstanceOf[this.type]
-}
-
-class LLCMSHRFile(sets: Int, ways: Int, outstanding: Int, refill_cycles: Int) extends Module
-{
-  val io = new Bundle {
-    val cpu = Decoupled(new MemReqCmd).flip
-    val repl_way = UInt(INPUT, log2Up(ways))
-    val repl_dirty = Bool(INPUT)
-    val repl_tag = UInt(INPUT, params(MIFAddrBits) - log2Up(sets))
-    val data = Decoupled(new LLCDataReq(ways))
-    val tag = Decoupled(new LLCTagReq(ways))
-    val mem = new MemPipeIO
-    val mem_resp_set = UInt(OUTPUT, log2Up(sets))
-    val mem_resp_way = UInt(OUTPUT, log2Up(ways))
-  }
-
-  class MSHR extends Bundle {
-    val addr = UInt(width = params(MIFAddrBits))
-    val way = UInt(width = log2Up(ways))
-    val tag = io.cpu.bits.tag.clone
-    val refilled = Bool()
-    val refillCount = UInt(width = log2Up(refill_cycles))
-    val requested = Bool()
-    val old_dirty = Bool()
-    val old_tag = UInt(width = params(MIFAddrBits) - log2Up(sets))
-    val wb_busy = Bool()
-
-    override def clone = new MSHR().asInstanceOf[this.type]
-  }
-
-  val valid = Vec.fill(outstanding){Reg(init=Bool(false))}
-  val validBits = valid.toBits
-  val freeId = PriorityEncoder(~validBits)
-  val mshr = Vec.fill(outstanding){Reg(new MSHR)}
-  when (io.cpu.valid && io.cpu.ready) {
-    valid(freeId) := Bool(true)
-    mshr(freeId).addr := io.cpu.bits.addr
-    mshr(freeId).tag := io.cpu.bits.tag
-    mshr(freeId).way := io.repl_way
-    mshr(freeId).old_dirty := io.repl_dirty
-    mshr(freeId).old_tag := io.repl_tag
-    mshr(freeId).wb_busy := Bool(false)
-    mshr(freeId).requested := Bool(false)
-    mshr(freeId).refillCount := UInt(0)
-    mshr(freeId).refilled := Bool(false)
-  }
-
-  val requests = Cat(Bits(0), (outstanding-1 to 0 by -1).map(i => valid(i) && !mshr(i).old_dirty && !mshr(i).wb_busy && !mshr(i).requested):_*)
-  val request = requests.orR && io.data.ready // allow in-flight hits to drain
-  val requestId = PriorityEncoder(requests)
-  when (io.mem.req_cmd.valid && io.mem.req_cmd.ready) { mshr(requestId).requested := Bool(true) }
-
-  val refillId = io.mem.resp.bits.tag(log2Up(outstanding)-1, 0)
-  val refillCount = mshr(refillId).refillCount
-  when (io.mem.resp.valid) {
-    mshr(refillId).refillCount := refillCount + UInt(1)
-    when (refillCount === UInt(refill_cycles-1)) { mshr(refillId).refilled := Bool(true) }
-  }
-
-  val replays = Cat(Bits(0), (outstanding-1 to 0 by -1).map(i => valid(i) && mshr(i).refilled):_*)
-  val replay = replays.orR
-  val replayId = PriorityEncoder(replays)
-  when (replay && io.data.ready && io.tag.ready) { valid(replayId) := Bool(false) }
-
-  val writebacks = Cat(Bits(0), (outstanding-1 to 0 by -1).map(i => valid(i) && mshr(i).old_dirty):_*)
-  val writeback = writebacks.orR
-  val writebackId = PriorityEncoder(writebacks)
-  when (writeback && io.data.ready && !replay) {
-    mshr(writebackId).old_dirty := Bool(false)
-    mshr(writebackId).wb_busy := Bool(true)
-  }
-  mshr.foreach(m => when (m.wb_busy && io.data.ready) { m.wb_busy := Bool(false) })
-
-  val conflicts = Cat(Bits(0), (0 until outstanding).map(i => valid(i) && io.cpu.bits.addr(log2Up(sets)-1, 0) === mshr(i).addr(log2Up(sets)-1, 0)):_*)
-  io.cpu.ready := !conflicts.orR && !validBits.andR
-
-  io.data.valid := writeback
-  io.data.bits.rw := Bool(false)
-  io.data.bits.tag := mshr(replayId).tag
-  io.data.bits.isWriteback := Bool(true)
-  io.data.bits.addr := Cat(mshr(writebackId).old_tag, mshr(writebackId).addr(log2Up(sets)-1, 0)).toUInt
-  io.data.bits.way := mshr(writebackId).way
-  when (replay) {
-    io.data.valid := io.tag.ready
-    io.data.bits.isWriteback := Bool(false)
-    io.data.bits.addr := mshr(replayId).addr
-    io.data.bits.way := mshr(replayId).way
-  }
-  io.tag.valid := replay && io.data.ready
-  io.tag.bits.addr := io.data.bits.addr
-  io.tag.bits.way := io.data.bits.way
-
-  io.mem.req_cmd.valid := request
-  io.mem.req_cmd.bits.rw := Bool(false)
-  io.mem.req_cmd.bits.addr := mshr(requestId).addr
-  io.mem.req_cmd.bits.tag := requestId
-  io.mem_resp_set := mshr(refillId).addr
-  io.mem_resp_way := mshr(refillId).way
-}
-
-class LLCWriteback(requestors: Int, refill_cycles: Int) extends Module
-{
-  val io = new Bundle {
-    val req = Vec.fill(requestors){Decoupled(UInt(width = params(MIFAddrBits))).flip }
-    val data = Vec.fill(requestors){Decoupled(new MemData).flip }
-    val mem = new MemPipeIO
-  }
-
-  val valid = Reg(init=Bool(false))
-  val who = Reg(UInt())
-  val addr = Reg(UInt())
-  val cmd_sent = Reg(Bool())
-  val data_sent = Reg(Bool())
-  val count = Reg(init=UInt(0, log2Up(refill_cycles)))
-
-  var anyReq = Bool(false)
-  for (i <- 0 until requestors) {
-    io.req(i).ready := !valid && !anyReq
-    io.data(i).ready := valid && who === UInt(i) && io.mem.req_data.ready
-    anyReq = anyReq || io.req(i).valid
-  }
-
-  val nextWho = PriorityEncoder(io.req.map(_.valid))
-  when (!valid && io.req.map(_.valid).reduceLeft(_||_)) {
-    valid := Bool(true)
-    cmd_sent := Bool(false)
-    data_sent := Bool(false)
-    who := nextWho
-    addr := io.req(nextWho).bits
-  }
-
-  when (io.mem.req_data.valid && io.mem.req_data.ready) {
-    count := count + UInt(1)
-    when (count === UInt(refill_cycles-1)) {
-      data_sent := Bool(true)
-      when (cmd_sent) { valid := Bool(false) }
-    }
-  }
-  when (io.mem.req_cmd.valid && io.mem.req_cmd.ready) { cmd_sent := Bool(true) }
-  when (valid && cmd_sent && data_sent) { valid := Bool(false) }
-
-  io.mem.req_cmd.valid := valid && !cmd_sent
-  io.mem.req_cmd.bits.addr := addr
-  io.mem.req_cmd.bits.rw := Bool(true)
-
-  io.mem.req_data.valid := valid && !data_sent && io.data(who).valid
-  io.mem.req_data.bits := io.data(who).bits
-}
-
-class LLCData(latency: Int, sets: Int, ways: Int, refill_cycles: Int, leaf: Mem[UInt]) extends Module
-{
-  val io = new Bundle {
-    val req = Decoupled(new LLCDataReq(ways)).flip
-    val req_data = Decoupled(new MemData).flip
-    val writeback = Decoupled(UInt(width = params(MIFAddrBits)))
-    val writeback_data = Decoupled(new MemData)
-    val resp = Decoupled(new MemResp)
-    val mem_resp = Valid(new MemResp).flip
-    val mem_resp_set = UInt(INPUT, log2Up(sets))
-    val mem_resp_way = UInt(INPUT, log2Up(ways))
-  }
-
-  val data = Module(new BigMem(sets*ways*refill_cycles, 1, latency-1, leaf, true)(Bits(width = params(MIFDataBits))))
-  class QEntry extends MemResp {
-    val isWriteback = Bool()
-    override def clone = new QEntry().asInstanceOf[this.type]
-  }
-  val q = Module(new Queue(new QEntry, latency+2))
-  val qReady = q.io.count <= UInt(q.entries-latency-1)
-  val valid = Reg(init=Bool(false))
-  val req = Reg(io.req.bits.clone)
-  val count = Reg(init=UInt(0, log2Up(refill_cycles)))
-  val refillCount = Reg(init=UInt(0, log2Up(refill_cycles)))
-
-  when (data.io.in.valid && !io.mem_resp.valid) {
-    count := count + UInt(1)
-    when (valid && count === UInt(refill_cycles-1)) { valid := Bool(false) }
-  }
-  when (io.req.valid && io.req.ready) { valid := Bool(true); req := io.req.bits }
-  when (io.mem_resp.valid) { refillCount := refillCount + UInt(1) }
-
-  data.io.in.valid := io.req.valid && io.req.ready && Mux(io.req.bits.rw, io.req_data.valid, qReady)
-  data.io.in.bits.addr := Cat(io.req.bits.way, io.req.bits.addr(log2Up(sets)-1, 0), count).toUInt
-  data.io.in.bits.rw := io.req.bits.rw
-  data.io.in.bits.wdata := io.req_data.bits.data
-  when (valid) {
-    data.io.in.valid := Mux(req.rw, io.req_data.valid, qReady)
-    data.io.in.bits.addr := Cat(req.way, req.addr(log2Up(sets)-1, 0), count).toUInt
-    data.io.in.bits.rw := req.rw
-  }
-  when (io.mem_resp.valid) {
-    data.io.in.valid := Bool(true)
-    data.io.in.bits.addr := Cat(io.mem_resp_way, io.mem_resp_set, refillCount).toUInt
-    data.io.in.bits.rw := Bool(true)
-    data.io.in.bits.wdata := io.mem_resp.bits.data
-  }
-
-  val tagPipe = Pipe(data.io.in.valid && !data.io.in.bits.rw, Mux(valid, req.tag, io.req.bits.tag), latency)
-  q.io.enq.valid := tagPipe.valid
-  q.io.enq.bits.tag := tagPipe.bits
-  q.io.enq.bits.isWriteback := Pipe(Mux(valid, req.isWriteback, io.req.bits.isWriteback), Bool(false), latency).valid
-  q.io.enq.bits.data := data.io.rdata
-
-  io.req.ready := !valid && Mux(io.req.bits.isWriteback, io.writeback.ready, Bool(true))
-  io.req_data.ready := !io.mem_resp.valid && Mux(valid, req.rw, io.req.valid && io.req.bits.rw)
-
-  io.writeback.valid := io.req.valid && io.req.ready && io.req.bits.isWriteback
-  io.writeback.bits := io.req.bits.addr
-
-  q.io.deq.ready := Mux(q.io.deq.bits.isWriteback, io.writeback_data.ready, io.resp.ready)
-  io.resp.valid := q.io.deq.valid && !q.io.deq.bits.isWriteback
-  io.resp.bits := q.io.deq.bits
-  io.writeback_data.valid := q.io.deq.valid && q.io.deq.bits.isWriteback
-  io.writeback_data.bits := q.io.deq.bits
-}
-
-class MemReqArb(n: Int, refill_cycles: Int) extends Module
-{
-  val io = new Bundle {
-    val cpu = Vec.fill(n){new MemIO().flip}
-    val mem = new MemIO
-  }
-
-  val lock = Reg(init=Bool(false))
-  val locker = Reg(UInt())
-
-  val arb = Module(new RRArbiter(new MemReqCmd, n))
-  val respWho = io.mem.resp.bits.tag(log2Up(n)-1,0)
-  val respTag = io.mem.resp.bits.tag >> UInt(log2Up(n))
-  for (i <- 0 until n) {
-    val me = UInt(i, log2Up(n))
-    arb.io.in(i).valid := io.cpu(i).req_cmd.valid
-    arb.io.in(i).bits := io.cpu(i).req_cmd.bits
-    arb.io.in(i).bits.tag := Cat(io.cpu(i).req_cmd.bits.tag, me)
-    io.cpu(i).req_cmd.ready := arb.io.in(i).ready
-    io.cpu(i).req_data.ready := Bool(false)
-
-    val getLock = io.cpu(i).req_cmd.fire() && io.cpu(i).req_cmd.bits.rw && !lock
-    val haveLock = lock && locker === me
-    when (getLock) {
-      lock := Bool(true)
-      locker := UInt(i)
-    }
-    when (getLock || haveLock) {
-      io.cpu(i).req_data.ready := io.mem.req_data.ready
-      io.mem.req_data.valid := Bool(true)
-      io.mem.req_data.bits := io.cpu(i).req_data.bits
-    }
-
-    io.cpu(i).resp.valid := io.mem.resp.valid && respWho === me
-    io.cpu(i).resp.bits := io.mem.resp.bits
-    io.cpu(i).resp.bits.tag := respTag
-  }
-  io.mem.resp.ready := io.cpu(respWho).resp.ready
-
-  val unlock = Counter(io.mem.req_data.fire(), refill_cycles)._2
-  when (unlock) { lock := Bool(false) }
-}
-
-abstract class DRAMSideLLCLike extends Module {
-  val io = new Bundle {
-    val cpu = new MemIO().flip
-    val mem = new MemPipeIO
-  }
-}
-
-// DRAMSideLLC has a known bug now. DO NOT USE. We are working on a brand new
-// L2$. Stay stuned.
-//
-// Bug description:
-// There's a race condition between the writeback unit (the module which
-// sends the data out to the backside interface) and the data unit (the module
-// which writes the data into the SRAM in the L2$).  The "hit status"
-// is saved in a register, however, is updated again when there's
-// a transaction coming from the core without waiting until the writeback unit
-// has sent out all its data to the outer memory system.  This is why the
-// problem manifests at a higher probability with the slow backup memory port.
-
-class DRAMSideLLC_HasKnownBug(sets: Int, ways: Int, outstanding: Int, refill_cycles: Int, tagLeaf: Mem[UInt], dataLeaf: Mem[UInt]) extends DRAMSideLLCLike
-{
-  val tagWidth = params(MIFAddrBits) - log2Up(sets)
-  val metaWidth = tagWidth + 2 // valid + dirty
-
-  val memCmdArb = Module(new Arbiter(new MemReqCmd, 2))
-  val dataArb = Module(new Arbiter(new LLCDataReq(ways), 2))
-  val mshr = Module(new LLCMSHRFile(sets, ways, outstanding, refill_cycles))
-  val tags = Module(new BigMem(sets, 0, 1, tagLeaf)(Bits(width = metaWidth*ways)))
-  val data = Module(new LLCData(4, sets, ways, refill_cycles, dataLeaf))
-  val writeback = Module(new LLCWriteback(2, refill_cycles))
-
-  val initCount = Reg(init=UInt(0, log2Up(sets+1)))
-  val initialize = !initCount(log2Up(sets))
-  when (initialize) { initCount := initCount + UInt(1) }
-
-  val replay_s2 = Reg(init=Bool(false))
-  val s2_valid = Reg(init=Bool(false))
-  val s2 = Reg(new MemReqCmd)
-  val s3_rdy = Bool()
-  val replay_s2_rdy = Bool()
-
-  val s1_valid = Reg(next = io.cpu.req_cmd.fire() || replay_s2 && replay_s2_rdy, init = Bool(false))
-  val s1 = Reg(new MemReqCmd)
-  when (io.cpu.req_cmd.fire()) { s1 := io.cpu.req_cmd.bits }
-  when (replay_s2 && replay_s2_rdy) { s1 := s2 }
-
-  s2_valid := s1_valid
-  replay_s2 := s2_valid && !s3_rdy || replay_s2 && !replay_s2_rdy
-  val s2_tags = Vec.fill(ways){Reg(Bits(width = metaWidth))}
-  when (s1_valid) {
-    s2 := s1
-    for (i <- 0 until ways)
-      s2_tags(i) := tags.io.rdata(metaWidth*(i+1)-1, metaWidth*i)
-  }
-  val s2_hits = s2_tags.map(t => t(tagWidth) && s2.addr(s2.addr.getWidth-1, s2.addr.getWidth-tagWidth) === t(tagWidth-1, 0))
-  val s2_hit_way = OHToUInt(s2_hits)
-  val s2_hit = s2_hits.reduceLeft(_||_)
-  val s2_hit_dirty = s2_tags(s2_hit_way)(tagWidth+1)
-  val repl_way = LFSR16(s2_valid)(log2Up(ways)-1, 0)
-  val repl_tag = s2_tags(repl_way).toUInt
-  val setDirty = s2_valid && s2.rw && s2_hit && !s2_hit_dirty
-
-  val tag_we = initialize || setDirty || mshr.io.tag.fire()
-  val tag_waddr = Mux(initialize, initCount, Mux(setDirty, s2.addr, mshr.io.tag.bits.addr))
-  val tag_wdata = Cat(setDirty, !initialize, Mux(setDirty, s2.addr, mshr.io.tag.bits.addr)(mshr.io.tag.bits.addr.getWidth-1, mshr.io.tag.bits.addr.getWidth-tagWidth))
-  val tag_wmask = Mux(initialize, SInt(-1, ways), UIntToOH(Mux(setDirty, s2_hit_way, mshr.io.tag.bits.way)))
-  tags.io.in.valid := io.cpu.req_cmd.fire() || replay_s2 && replay_s2_rdy || tag_we
-  tags.io.in.bits.addr := Mux(tag_we, tag_waddr, Mux(replay_s2, s2.addr, io.cpu.req_cmd.bits.addr)(log2Up(sets)-1,0))
-  tags.io.in.bits.rw := tag_we
-  tags.io.in.bits.wdata := Fill(ways, tag_wdata)
-  tags.io.in.bits.wmask := FillInterleaved(metaWidth, tag_wmask)
-
-  mshr.io.cpu.valid := s2_valid && !s2_hit && !s2.rw
-  mshr.io.cpu.bits := s2
-  mshr.io.repl_way := repl_way
-  mshr.io.repl_dirty := repl_tag(tagWidth+1, tagWidth).andR
-  mshr.io.repl_tag := repl_tag
-  mshr.io.mem.resp := io.mem.resp
-  mshr.io.tag.ready := !s1_valid && !s2_valid
-
-  data.io.req <> dataArb.io.out
-  data.io.mem_resp := io.mem.resp
-  data.io.mem_resp_set := mshr.io.mem_resp_set
-  data.io.mem_resp_way := mshr.io.mem_resp_way
-  data.io.req_data.bits := io.cpu.req_data.bits
-  data.io.req_data.valid := io.cpu.req_data.valid
-
-  writeback.io.req(0) <> data.io.writeback
-  writeback.io.data(0) <> data.io.writeback_data
-  writeback.io.req(1).valid := s2_valid && !s2_hit && s2.rw && mshr.io.cpu.ready
-  writeback.io.req(1).bits := s2.addr
-  writeback.io.data(1).valid := io.cpu.req_data.valid
-  writeback.io.data(1).bits := io.cpu.req_data.bits
-
-  memCmdArb.io.in(0) <> mshr.io.mem.req_cmd
-  memCmdArb.io.in(1) <> writeback.io.mem.req_cmd
-
-  dataArb.io.in(0) <> mshr.io.data
-  dataArb.io.in(1).valid := s2_valid && s2_hit && mshr.io.cpu.ready
-  dataArb.io.in(1).bits := s2
-  dataArb.io.in(1).bits.way := s2_hit_way
-  dataArb.io.in(1).bits.isWriteback := Bool(false)
-
-  s3_rdy := mshr.io.cpu.ready && Mux(s2_hit, dataArb.io.in(1).ready, !s2.rw || writeback.io.req(1).ready)
-  replay_s2_rdy := s3_rdy && !tag_we
-
-  io.cpu.resp <> data.io.resp
-  io.cpu.req_data.ready := writeback.io.data(1).ready || data.io.req_data.ready
-  io.mem.req_cmd <> memCmdArb.io.out
-  io.mem.req_data <> writeback.io.mem.req_data
-  io.cpu.req_cmd.ready := !(s1_valid || s2_valid || replay_s2 || tag_we ||
-    io.cpu.req_cmd.bits.rw && io.cpu.req_data.ready)
-}
-
-class HellaFlowQueue[T <: Data](val entries: Int)(data: => T) extends Module
-{
-  val io = new QueueIO(data, entries)
-  require(isPow2(entries) && entries > 1)
-
-  val do_flow = Bool()
-  val do_enq = io.enq.fire() && !do_flow
-  val do_deq = io.deq.fire() && !do_flow
-
-  val maybe_full = Reg(init=Bool(false))
-  val enq_ptr = Counter(do_enq, entries)._1
-  val deq_ptr = Counter(do_deq, entries)._1
-  when (do_enq != do_deq) { maybe_full := do_enq }
-
-  val ptr_match = enq_ptr === deq_ptr
-  val empty = ptr_match && !maybe_full
-  val full = ptr_match && maybe_full
-  val atLeastTwo = full || enq_ptr - deq_ptr >= UInt(2)
-  do_flow := empty && io.deq.ready
-
-  val ram = Mem(data, entries, seqRead = true)
-  val ram_addr = Reg(Bits())
-  val ram_out_valid = Reg(Bool())
-  ram_out_valid := Bool(false)
-  when (do_enq) { ram(enq_ptr) := io.enq.bits }
-  when (io.deq.ready && (atLeastTwo || !io.deq.valid && !empty)) {
-    ram_out_valid := Bool(true)
-    ram_addr := Mux(io.deq.valid, deq_ptr + UInt(1), deq_ptr)
-  }
-
-  io.deq.valid := Mux(empty, io.enq.valid, ram_out_valid)
-  io.enq.ready := !full
-  io.deq.bits := Mux(empty, io.enq.bits, ram(ram_addr))
-}
-
-class HellaQueue[T <: Data](val entries: Int)(data: => T) extends Module
-{
-  val io = new QueueIO(data, entries)
-
-  val fq = Module(new HellaFlowQueue(entries)(data))
-  io.enq <> fq.io.enq
-  io.deq <> Queue(fq.io.deq, 1, pipe = true)
-}
-
-object HellaQueue
-{
-  def apply[T <: Data](enq: DecoupledIO[T], entries: Int) = {
-    val q = Module((new HellaQueue(entries)) { enq.bits.clone })
-    q.io.enq.valid := enq.valid // not using <> so that override is allowed
-    q.io.enq.bits := enq.bits
-    enq.ready := q.io.enq.ready
-    q.io.deq
-  }
-}
-
-class DRAMSideLLCNull(numRequests: Int, refillCycles: Int) extends DRAMSideLLCLike {
-  val numEntries = numRequests * refillCycles
-  val size = log2Down(numEntries) + 1
-
-  val inc = Bool()
-  val dec = Bool()
-  val count = Reg(init=UInt(numEntries, size))
-  val watermark = count >= UInt(refillCycles)
-
-  when (inc && !dec) {
-    count := count + UInt(1)
-  }
-  when (!inc && dec) {
-    count := count - UInt(refillCycles)
-  }
-  when (inc && dec) {
-    count := count - UInt(refillCycles-1)
-  }
-
-  val cmdq_mask = io.cpu.req_cmd.bits.rw || watermark
-
-  io.mem.req_cmd.valid := io.cpu.req_cmd.valid && cmdq_mask
-  io.cpu.req_cmd.ready := io.mem.req_cmd.ready && cmdq_mask
-  io.mem.req_cmd.bits := io.cpu.req_cmd.bits
-
-  io.mem.req_data <> io.cpu.req_data
-
-  val resp_dataq = Module((new HellaQueue(numEntries)) { new MemResp })
-  resp_dataq.io.enq <> io.mem.resp
-  io.cpu.resp <> resp_dataq.io.deq
-
-  inc := resp_dataq.io.deq.fire()
-  dec := io.mem.req_cmd.fire() && !io.mem.req_cmd.bits.rw
-}

uncore/src/main/scala/memserdes.scala

@@ -286,3 +286,112 @@ class MemIOUncachedTileLinkIOConverter(qDepth: Int) extends Module {
   }
 }
 
+class HellaFlowQueue[T <: Data](val entries: Int)(data: => T) extends Module
+{
+  val io = new QueueIO(data, entries)
+  require(isPow2(entries) && entries > 1)
+
+  val do_flow = Bool()
+  val do_enq = io.enq.fire() && !do_flow
+  val do_deq = io.deq.fire() && !do_flow
+
+  val maybe_full = Reg(init=Bool(false))
+  val enq_ptr = Counter(do_enq, entries)._1
+  val deq_ptr = Counter(do_deq, entries)._1
+  when (do_enq != do_deq) { maybe_full := do_enq }
+
+  val ptr_match = enq_ptr === deq_ptr
+  val empty = ptr_match && !maybe_full
+  val full = ptr_match && maybe_full
+  val atLeastTwo = full || enq_ptr - deq_ptr >= UInt(2)
+  do_flow := empty && io.deq.ready
+
+  val ram = Mem(data, entries, seqRead = true)
+  val ram_addr = Reg(Bits())
+  val ram_out_valid = Reg(Bool())
+  ram_out_valid := Bool(false)
+  when (do_enq) { ram(enq_ptr) := io.enq.bits }
+  when (io.deq.ready && (atLeastTwo || !io.deq.valid && !empty)) {
+    ram_out_valid := Bool(true)
+    ram_addr := Mux(io.deq.valid, deq_ptr + UInt(1), deq_ptr)
+  }
+
+  io.deq.valid := Mux(empty, io.enq.valid, ram_out_valid)
+  io.enq.ready := !full
+  io.deq.bits := Mux(empty, io.enq.bits, ram(ram_addr))
+}
+
+class HellaQueue[T <: Data](val entries: Int)(data: => T) extends Module
+{
+  val io = new QueueIO(data, entries)
+
+  val fq = Module(new HellaFlowQueue(entries)(data))
+  io.enq <> fq.io.enq
+  io.deq <> Queue(fq.io.deq, 1, pipe = true)
+}
+
+object HellaQueue
+{
+  def apply[T <: Data](enq: DecoupledIO[T], entries: Int) = {
+    val q = Module((new HellaQueue(entries)) { enq.bits.clone })
+    q.io.enq.valid := enq.valid // not using <> so that override is allowed
+    q.io.enq.bits := enq.bits
+    enq.ready := q.io.enq.ready
+    q.io.deq
+  }
+}
+
+class MemPipeIOMemIOConverter(numRequests: Int, refillCycles: Int) extends Module {
+  val io = new Bundle {
+    val cpu = new MemIO().flip
+    val mem = new MemPipeIO
+  }
+
+  val numEntries = numRequests * refillCycles
+  val size = log2Down(numEntries) + 1
+
+  val inc = Bool()
+  val dec = Bool()
+  val count = Reg(init=UInt(numEntries, size))
+  val watermark = count >= UInt(refillCycles)
+
+  when (inc && !dec) {
+    count := count + UInt(1)
+  }
+  when (!inc && dec) {
+    count := count - UInt(refillCycles)
+  }
+  when (inc && dec) {
+    count := count - UInt(refillCycles-1)
+  }
+
+  val cmdq_mask = io.cpu.req_cmd.bits.rw || watermark
+
+  io.mem.req_cmd.valid := io.cpu.req_cmd.valid && cmdq_mask
+  io.cpu.req_cmd.ready := io.mem.req_cmd.ready && cmdq_mask
+  io.mem.req_cmd.bits := io.cpu.req_cmd.bits
+
+  io.mem.req_data <> io.cpu.req_data
+
+  val resp_dataq = Module((new HellaQueue(numEntries)) { new MemResp })
+  resp_dataq.io.enq <> io.mem.resp
+  io.cpu.resp <> resp_dataq.io.deq
+
+  inc := resp_dataq.io.deq.fire()
+  dec := io.mem.req_cmd.fire() && !io.mem.req_cmd.bits.rw
+}
+
+class MemPipeIOUncachedTileLinkIOConverter(outstanding: Int, refillCycles: Int) extends Module {
+  val io = new Bundle {
+    val uncached = new UncachedTileLinkIO().flip
+    val mem = new MemPipeIO
+  }
+  
+  val a = Module(new MemIOUncachedTileLinkIOConverter(2))
+  val b = Module(new MemPipeIOMemIOConverter(outstanding, refillCycles))
+  a.io.uncached <> io.uncached
+  b.io.cpu.req_cmd <> Queue(a.io.mem.req_cmd, 2)
+  b.io.cpu.req_data <> Queue(a.io.mem.req_data, refillCycles)
+  a.io.mem.resp <> b.io.cpu.resp
+  b.io.mem <> io.mem
+}