riscv/rocket-chip
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rocket: don't remove ports on top module

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This commit is contained in:
Henry Cook
2017-10-05 16:29:16 -07:00
committed by Wesley W. Terpstra
parent 5ff4c1674a
commit 75345b6048
3 changed files with 19 additions and 0 deletions
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2
src/main/scala/system/ExampleRocketSystem.scala
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@ -6,6 +6,7 @@ import Chisel._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.coreplex._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.util.DontTouch
/** Example Top with periphery devices and ports, and a Rocket coreplex */
class ExampleRocketSystem(implicit p: Parameters) extends RocketCoreplex
@ -25,3 +26,4 @@ class ExampleRocketSystemModule[+L <: ExampleRocketSystem](_outer: L) extends Ro
with HasMasterAXI4MMIOPortModuleImp
with HasSlaveAXI4PortModuleImp
with HasPeripheryBootROMModuleImp
with DontTouch

1
src/main/scala/system/TestHarness.scala
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@ -14,6 +14,7 @@ class TestHarness()(implicit p: Parameters) extends Module {
val dut = Module(LazyModule(new ExampleRocketSystem).module)
dut.reset := reset | dut.debug.ndreset
dut.dontTouchPorts()
dut.tieOffInterrupts()
dut.connectSimAXIMem()
dut.connectSimAXIMMIO()