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JTAG: Revert to Chisel._ for Issue 1160 (#1161)

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* JTAG: Revert to Chisel._ for Issue 1160

* JTAG: Revert to Chisel._ for Issue 1160

* jtag: revert everything to Chisel._

* jtag: Revert all modules to Chisel._ vs chisel3, due to FIRRTL issues with chisel3 generated code
This commit is contained in:
Megan Wachs 2017-12-18 21:02:31 -08:00 committed by GitHub
parent a31ba2ea2e
commit 74d9326ebc
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 22 additions and 13 deletions
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5
src/main/scala/jtag/JtagShifter.scala
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@ -2,10 +2,11 @@
package freechips.rocketchip.jtag
import chisel3._
//import chisel3._
import Chisel._
import chisel3.core.{Input, Output}
import chisel3.core.DataMirror
import chisel3.internal.firrtl.KnownWidth
import chisel3.util._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.util.property._

7
src/main/scala/jtag/JtagStateMachine.scala
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@ -2,8 +2,8 @@
package freechips.rocketchip.jtag
import chisel3._
import chisel3.util._
import Chisel._
import chisel3.{Input, Output}
import freechips.rocketchip.config.{Parameters}
import freechips.rocketchip.util.{AsyncResetRegVec}
import freechips.rocketchip.util.property._
@ -78,7 +78,8 @@ class JtagStateMachine(implicit val p: Parameters) extends Module(override_reset
}
val io = IO(new StateMachineIO)
val nextState = WireInit(JtagState.State.chiselType(), DontCare)
// val nextState = WireInit(JtagState.State.chiselType(), DontCare)
val nextState = Wire(JtagState.State.chiselType())
val currStateReg = Module (new AsyncResetRegVec(w = JtagState.State.width,
init = JtagState.State.toInt(JtagState.TestLogicReset)))

15
src/main/scala/jtag/JtagTap.scala
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@ -4,7 +4,10 @@ package freechips.rocketchip.jtag
import scala.collection.SortedMap
import chisel3._
// !!! See Issue #1160.
// import chisel3._
import Chisel._
import chisel3.core.{Input, Output}
import chisel3.util._
import freechips.rocketchip.config.Parameters
@ -111,7 +114,8 @@ class JtagTapController(irLength: Int, initialInstruction: BigInt)(implicit val
nextActiveInstruction := irChain.io.update.bits
updateInstruction := true.B
} .otherwise {
nextActiveInstruction := DontCare
//!!! Needed when using chisel3._ (See #1160)
// nextActiveInstruction := DontCare
updateInstruction := false.B
}
io.output.instruction := activeInstruction
@ -136,7 +140,8 @@ class JtagTapController(irLength: Int, initialInstruction: BigInt)(implicit val
tdo := irChain.io.chainOut.data
tdo_driven := true.B
} .otherwise {
tdo := DontCare
//!!! Needed when using chisel3._ (See #1160)
//tdo := DontCare
tdo_driven := false.B
}
}
@ -247,8 +252,8 @@ object JtagTapGenerator {
chainToSelect.map(mapInSelect)
controllerInternal.io.jtag <> internalIo.jtag
controllerInternal.io.control <> internalIo.control
controllerInternal.io.output <> internalIo.output
internalIo.control <> controllerInternal.io.control
internalIo.output <> controllerInternal.io.output
internalIo
}

3
src/main/scala/jtag/JtagUtils.scala
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@ -2,7 +2,8 @@
package freechips.rocketchip.jtag
import chisel3._
import Chisel._
//import chisel3._
import chisel3.util._
class JTAGIdcodeBundle extends Bundle {

5
src/main/scala/jtag/Utils.scala
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@ -2,8 +2,9 @@
package freechips.rocketchip.jtag
import chisel3._
import chisel3.util._
//import chisel3._
import Chisel._
import chisel3.core.{Input, Output}
/** Bundle representing a tristate pin.
*/