Improve BTB critical path at slight accuracy cost
Make entries fully associative on lower 14 bits only, not full address.
This commit is contained in:
Andrew Waterman
parent
11c8857b5d
commit
74d8d672bf
@ -11,16 +11,18 @@ import util._
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case class BTBParams(
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nEntries: Int = 40,
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nMatchBits: Int = 14,
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nPages: Int = 6,
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nRAS: Int = 2,
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updatesOutOfOrder: Boolean = false)
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trait HasBtbParameters extends HasCoreParameters {
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val btbParams = tileParams.btb.getOrElse(BTBParams(nEntries = 0))
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val matchBits = pgIdxBits max log2Ceil(p(coreplex.CacheBlockBytes) * tileParams.icache.get.nSets)
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val matchBits = btbParams.nMatchBits max log2Ceil(p(coreplex.CacheBlockBytes) * tileParams.icache.get.nSets)
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val entries = btbParams.nEntries
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val nRAS = btbParams.nRAS
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val updatesOutOfOrder = btbParams.updatesOutOfOrder
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val nPages = ((1 max(log2Up(entries)))+1)/2*2 // control logic assumes 2 divides pages
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val nPages = (btbParams.nPages + 1) / 2 * 2 // control logic assumes 2 divides pages
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val opaqueBits = log2Up(entries)
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val nBHT = 1 << log2Up(entries*2)
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}
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@ -150,8 +152,6 @@ class BTB(implicit p: Parameters) extends BtbModule {
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val tgtPages = Reg(Vec(entries, UInt(width=log2Up(nPages))))
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val pages = Reg(Vec(nPages, UInt(width=vaddrBits - matchBits)))
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val pageValid = Reg(init = UInt(0, nPages))
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val idxPagesOH = idxPages.map(UIntToOH(_)(nPages-1,0))
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val tgtPagesOH = tgtPages.map(UIntToOH(_)(nPages-1,0))
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val isValid = Reg(init = UInt(0, entries))
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val isReturn = Reg(UInt(width = entries))
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@ -163,31 +163,29 @@ class BTB(implicit p: Parameters) extends BtbModule {
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val p = page(addr)
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pageValid & pages.map(_ === p).asUInt
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}
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private def tagMatch(addr: UInt, pgMatch: UInt) = {
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val idxMatch = idxs.map(_ === addr(matchBits-1, log2Up(coreInstBytes))).asUInt
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val idxPageMatch = idxPagesOH.map(_ & pgMatch).map(_.orR).asUInt
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idxMatch & idxPageMatch & isValid
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private def idxMatch(addr: UInt) = {
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val idx = addr(matchBits-1, log2Up(coreInstBytes))
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idxs.map(_ === idx).asUInt & isValid
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}
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val r_btb_update = Pipe(io.btb_update)
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val update_target = io.req.bits.addr
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val pageHit = pageMatch(io.req.bits.addr)
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val hitsVec = tagMatch(io.req.bits.addr, pageHit)
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val hits = hitsVec.asUInt
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val idxHit = idxMatch(io.req.bits.addr)
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val updatePageHit = pageMatch(r_btb_update.bits.pc)
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val updateHits = tagMatch(r_btb_update.bits.pc, updatePageHit)
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val updateHit = if (updatesOutOfOrder) updateHits.orR else r_btb_update.bits.prediction.valid
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val updateHitAddr = if (updatesOutOfOrder) OHToUInt(updateHits) else r_btb_update.bits.prediction.bits.entry
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val nextRepl = Counter(r_btb_update.valid && !updateHit, entries)._1
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val (updateHit, updateHitAddr) =
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if (updatesOutOfOrder) {
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val updateHits = (pageHit << 1)(Mux1H(idxMatch(r_btb_update.bits.pc), idxPages))
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(updateHits.orR, OHToUInt(updateHits))
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} else (r_btb_update.bits.prediction.valid, r_btb_update.bits.prediction.bits.entry)
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val useUpdatePageHit = updatePageHit.orR
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val usePageHit = pageHit.orR
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val doIdxPageRepl = !useUpdatePageHit
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val nextPageRepl = Reg(UInt(width = log2Ceil(nPages)))
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val idxPageRepl = Mux(usePageHit, Cat(pageHit(nPages-2,0), pageHit(nPages-1)), UIntToOH(nextPageRepl))
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val idxPageRepl = Cat(pageHit(nPages-2,0), pageHit(nPages-1)) | Mux(usePageHit, UInt(0), UIntToOH(nextPageRepl))
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val idxPageUpdateOH = Mux(useUpdatePageHit, updatePageHit, idxPageRepl)
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val idxPageUpdate = OHToUInt(idxPageUpdateOH)
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val idxPageReplEn = Mux(doIdxPageRepl, idxPageRepl, UInt(0))
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@ -195,7 +193,7 @@ class BTB(implicit p: Parameters) extends BtbModule {
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val samePage = page(r_btb_update.bits.pc) === page(update_target)
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val doTgtPageRepl = !samePage && !usePageHit
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val tgtPageRepl = Mux(samePage, idxPageUpdateOH, Cat(idxPageUpdateOH(nPages-2,0), idxPageUpdateOH(nPages-1)))
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val tgtPageUpdate = OHToUInt(Mux(usePageHit, pageHit, tgtPageRepl))
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val tgtPageUpdate = OHToUInt(pageHit | Mux(usePageHit, UInt(0), tgtPageRepl))
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val tgtPageReplEn = Mux(doTgtPageRepl, tgtPageRepl, UInt(0))
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when (r_btb_update.valid && (doIdxPageRepl || doTgtPageRepl)) {
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@ -205,11 +203,12 @@ class BTB(implicit p: Parameters) extends BtbModule {
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}
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when (r_btb_update.valid) {
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val nextRepl = Counter(r_btb_update.valid && !updateHit, entries)._1
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val waddr = Mux(updateHit, updateHitAddr, nextRepl)
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val mask = UIntToOH(waddr)
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idxs(waddr) := r_btb_update.bits.pc(matchBits-1, log2Up(coreInstBytes))
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tgts(waddr) := update_target(matchBits-1, log2Up(coreInstBytes))
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idxPages(waddr) := idxPageUpdate
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idxPages(waddr) := idxPageUpdate +& 1 // the +1 corresponds to the <<1 on io.resp.valid
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tgtPages(waddr) := tgtPageUpdate
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isValid := Mux(r_btb_update.bits.isValid, isValid | mask, isValid & ~mask)
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isReturn := Mux(r_btb_update.bits.isReturn, isReturn | mask, isReturn & ~mask)
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@ -231,21 +230,21 @@ class BTB(implicit p: Parameters) extends BtbModule {
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pageValid := pageValid | tgtPageReplEn | idxPageReplEn
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}
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io.resp.valid := hits.orR
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io.resp.valid := (pageHit << 1)(Mux1H(idxHit, idxPages))
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io.resp.bits.taken := true
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io.resp.bits.target := Cat(Mux1H(Mux1H(hitsVec, tgtPagesOH), pages), Mux1H(hitsVec, tgts) << log2Up(coreInstBytes))
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io.resp.bits.entry := OHToUInt(hits)
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io.resp.bits.bridx := (if (fetchWidth > 1) Mux1H(hitsVec, brIdx) else UInt(0))
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io.resp.bits.target := Cat(pages(Mux1H(idxHit, tgtPages)), Mux1H(idxHit, tgts) << log2Up(coreInstBytes))
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io.resp.bits.entry := OHToUInt(idxHit)
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io.resp.bits.bridx := (if (fetchWidth > 1) Mux1H(idxHit, brIdx) else UInt(0))
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io.resp.bits.mask := Cat((UInt(1) << ~Mux(io.resp.bits.taken, ~io.resp.bits.bridx, UInt(0)))-1, UInt(1))
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// if multiple entries for same PC land in BTB, zap them
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when (PopCountAtLeast(hits, 2)) {
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isValid := isValid & ~hits
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when (PopCountAtLeast(idxHit, 2)) {
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isValid := isValid & ~idxHit
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}
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if (nBHT > 0) {
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val bht = new BHT(nBHT)
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val isBranch = !(hits & isJump).orR
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val isBranch = !(idxHit & isJump).orR
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val res = bht.get(io.req.bits.addr, io.req.valid && io.resp.valid && isBranch)
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val update_btb_hit = io.bht_update.bits.prediction.valid
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when (io.bht_update.valid && update_btb_hit) {
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@ -257,7 +256,7 @@ class BTB(implicit p: Parameters) extends BtbModule {
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if (nRAS > 0) {
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val ras = new RAS(nRAS)
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val doPeek = (hits & isReturn).orR
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val doPeek = (idxHit & isReturn).orR
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when (!ras.isEmpty && doPeek) {
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io.resp.bits.target := ras.peek
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}
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@ -80,6 +80,7 @@ class IBuf(implicit p: Parameters) extends CoreModule {
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val xcpt_if = valid & (Mux(buf.xcpt_if, bufMask, UInt(0)) | Mux(io.imem.bits.xcpt_if, ~bufMask, UInt(0)))
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val ic_replay = valid & (Mux(buf.replay, bufMask, UInt(0)) | Mux(io.imem.bits.replay, ~bufMask, UInt(0)))
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val ibufBTBHitMask = Mux(ibufBTBHit, UIntToOH(ibufBTBResp.bridx), UInt(0))
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assert(!io.imem.bits.btb.valid || io.imem.bits.btb.bits.bridx >= pcWordBits)
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val icBTBHitMask = Mux(io.imem.bits.btb.valid, UIntToOH(io.imem.bits.btb.bits.bridx +& nBufValid - pcWordBits), UInt(0))
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val btbHitMask = ibufBTBHitMask & bufMask | icBTBHitMask & ~bufMask
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