riscv/rocket-chip
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Improve BTB critical path at slight accuracy cost

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Make entries fully associative on lower 14 bits only, not full address.
This commit is contained in:
Andrew Waterman
2017-03-05 23:01:07 -08:00
parent 11c8857b5d
commit 74d8d672bf
2 changed files with 27 additions and 27 deletions
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src/main/scala/rocket/IBuf.scala
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@ -80,6 +80,7 @@ class IBuf(implicit p: Parameters) extends CoreModule {
val xcpt_if = valid & (Mux(buf.xcpt_if, bufMask, UInt(0)) | Mux(io.imem.bits.xcpt_if, ~bufMask, UInt(0)))
val ic_replay = valid & (Mux(buf.replay, bufMask, UInt(0)) | Mux(io.imem.bits.replay, ~bufMask, UInt(0)))
val ibufBTBHitMask = Mux(ibufBTBHit, UIntToOH(ibufBTBResp.bridx), UInt(0))
assert(!io.imem.bits.btb.valid || io.imem.bits.btb.bits.bridx >= pcWordBits)
val icBTBHitMask = Mux(io.imem.bits.btb.valid, UIntToOH(io.imem.bits.btb.bits.bridx +& nBufValid - pcWordBits), UInt(0))
val btbHitMask = ibufBTBHitMask & bufMask | icBTBHitMask & ~bufMask