From 74cd588c65a90407fe094aa42bd3fc2b0d39dc79 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Tue, 28 Jun 2016 13:16:48 -0700
Subject: [PATCH] refactor uncore to split into separate packages

---
 groundtest                       | 2 +-
 rocket                           | 2 +-
 src/main/scala/Configs.scala     | 5 ++++-
 src/main/scala/Fpga.scala        | 2 +-
 src/main/scala/RocketChip.scala  | 7 ++++++-
 src/main/scala/TestBench.scala   | 2 +-
 src/main/scala/TestConfigs.scala | 5 ++++-
 uncore                           | 2 +-
 8 files changed, 19 insertions(+), 8 deletions(-)

diff --git a/groundtest b/groundtest
index 074d444f..7bfbda6b 160000
--- a/groundtest
+++ b/groundtest
@@ -1 +1 @@
-Subproject commit 074d444f02d6edf8905ecc4feb20763c37f9a767
+Subproject commit 7bfbda6bdc32e00ecd54608307f1f9baf3920245
diff --git a/rocket b/rocket
index 36e02ac9..ab876413 160000
--- a/rocket
+++ b/rocket
@@ -1 +1 @@
-Subproject commit 36e02ac94a8b2fbaa057bee37b2f7ed2a72dd227
+Subproject commit ab87641325372344d8012751f8ac9f433cdeee50
diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index 3d29fb8b..62933bfb 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -4,7 +4,10 @@ package rocketchip
 
 import Chisel._
 import junctions._
-import uncore._
+import uncore.tilelink._
+import uncore.coherence._
+import uncore.agents._
+import uncore.devices._
 import rocket._
 import rocket.Util._
 import groundtest._
diff --git a/src/main/scala/Fpga.scala b/src/main/scala/Fpga.scala
index b45115ce..6105a925 100644
--- a/src/main/scala/Fpga.scala
+++ b/src/main/scala/Fpga.scala
@@ -1,7 +1,7 @@
 package rocketchip
 
 import Chisel._
-import uncore._
+import uncore.tilelink._
 import junctions._
 import cde.Parameters
 
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index a02f891e..2f28df88 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -5,7 +5,12 @@ package rocketchip
 import Chisel._
 import cde.{Parameters, Field}
 import junctions._
-import uncore._
+import uncore.tilelink._
+import uncore.coherence._
+import uncore.agents._
+import uncore.devices._
+import uncore.util._
+import uncore.converters._
 import rocket._
 import rocket.Util._
 
diff --git a/src/main/scala/TestBench.scala b/src/main/scala/TestBench.scala
index 07cb3396..68591e0f 100644
--- a/src/main/scala/TestBench.scala
+++ b/src/main/scala/TestBench.scala
@@ -4,7 +4,7 @@ package rocketchip
 
 import Chisel._
 import cde.Parameters
-import uncore.{DbBusConsts, DMKey}
+import uncore.devices.{DbBusConsts, DMKey}
 
 object TestBenchGeneration extends FileSystemUtilities {
   def generateVerilogFragment(
diff --git a/src/main/scala/TestConfigs.scala b/src/main/scala/TestConfigs.scala
index 9531a650..1b5a85cf 100644
--- a/src/main/scala/TestConfigs.scala
+++ b/src/main/scala/TestConfigs.scala
@@ -3,7 +3,10 @@ package rocketchip
 import Chisel._
 import groundtest._
 import rocket._
-import uncore._
+import uncore.tilelink._
+import uncore.coherence._
+import uncore.agents._
+import uncore.devices.NTiles
 import junctions._
 import scala.collection.mutable.LinkedHashSet
 import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
diff --git a/uncore b/uncore
index 99f0c8dc..acc61673 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit 99f0c8dcae783d19ed5d1192b4d658bcc2b65e5a
+Subproject commit acc61673a6455320b7a01b74df41c5c453510823