RegFieldDesc: Update reg field descs to be more correct for devices.

src/main/scala/devices/debug/Debug.scala

@@ -254,7 +254,8 @@ object WNotifyWire {
       set := valid
       value := data
       Bool(true)
-    }), Some(RegFieldDesc(name = name, desc = desc, access = RegFieldAccessType.WSPECIAL)))
+    }), Some(RegFieldDesc(name = name, desc = desc,
+      access = RegFieldAccessType.W)))
   }
 }
 
@@ -898,12 +899,13 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
         programBufferMem.zipWithIndex.map {case (x, i) => RegField(8, x, RegFieldDesc(s"debug_progbuf_$i", ""))}),
 
       // These sections are read-only.
-      IMPEBREAK(cfg)-> {if (cfg.hasImplicitEbreak) Seq(RegField.r(32,  Instructions.EBREAK.value.U, RegFieldDesc("debug_impebreak", "Debug Implicit EBREAK"))) else Nil},
+      IMPEBREAK(cfg)-> {if (cfg.hasImplicitEbreak) Seq(RegField.r(32,  Instructions.EBREAK.value.U,
-      WHERETO       -> Seq(RegField.r(32, jalAbstract.asUInt, RegFieldDesc("debug_whereto", "Instruction filled in by Debug Module to control hart in Debug Mode"))),
+        RegFieldDesc("debug_impebreak", "Debug Implicit EBREAK", reset=Some(Instructions.EBREAK.value)))) else Nil},
+      WHERETO       -> Seq(RegField.r(32, jalAbstract.asUInt, RegFieldDesc("debug_whereto", "Instruction filled in by Debug Module to control hart in Debug Mode", volatile = true))),
       ABSTRACT(cfg) -> RegFieldGroup("debug_abstract", Some("Instructions generated by Debug Module"),
-        abstractGeneratedMem.zipWithIndex.map{ case (x,i) => RegField.r(32, x, RegFieldDesc(s"debug_abstract_$i", ""))}),
+        abstractGeneratedMem.zipWithIndex.map{ case (x,i) => RegField.r(32, x, RegFieldDesc(s"debug_abstract_$i", "", volatile=true))}),
       FLAGS         -> RegFieldGroup("debug_flags", Some("Memory region used to control hart going/resuming in Debug Mode"),
-        flags.zipWithIndex.map{case(x, i) => RegField.r(8, x.asUInt(), RegFieldDesc(s"debug_flags_${i}", ""))}),
+        flags.zipWithIndex.map{case(x, i) => RegField.r(8, x.asUInt(), RegFieldDesc(s"debug_flags_${i}", "", volatile=true))}),
       ROMBASE       -> RegFieldGroup("debug_rom", Some("Debug ROM"),
         DebugRomContents().zipWithIndex.map{case (x, i) => RegField.r(8, (x & 0xFF).U(8.W),
           RegFieldDesc(s"debug_rom_$i", "", reset=Some(x)))})

src/main/scala/devices/tilelink/Plic.scala

@@ -170,14 +170,16 @@ class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends
 
     def priorityRegDesc(i: Int) = if (i > 0) {
       RegFieldDesc(s"priority_$i", s"Acting priority of interrupt source $i",
-        reset=if (nPriorities > 0) None else Some(1), access=RegFieldAccessType.RWSPECIAL)
+        reset=if (nPriorities > 0) None else Some(1),
+        wrType=Some(RegFieldWrType.MODIFY))
     } else {
-      RegFieldDesc("reserved", "", reset=Some(0), access=RegFieldAccessType.R)
+      RegFieldDescReserved()
     }
     def pendingRegDesc(i: Int) = if (i > 0) {
-      RegFieldDesc(s"pending_$i", s"Set to 1 if interrupt source $i is pending, regardless of its enable or priority setting.")
+      RegFieldDesc(s"pending_$i", s"Set to 1 if interrupt source $i is pending, regardless of its enable or priority setting.",
+      volatile = true)
     } else {
-      RegFieldDesc("reserved", "", reset=Some(0), access=RegFieldAccessType.R)
+      RegFieldDescReserved()
     }
 
     def priorityRegField(x: UInt, i: Int) = if (nPriorities > 0) RegField(32, x, priorityRegDesc(i)) else RegField.r(32, x, priorityRegDesc(i))
@@ -193,7 +195,7 @@ class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends
         e.zipWithIndex.map{case (b, j) => if (j > 0) {
           RegField(1, b, RegFieldDesc(s"enable_${i}_${j}", s"Enable interrupt for source $j for target $i.", reset=None))
         } else {
-          RegField(1, b, RegFieldDesc("reserved", "", reset=Some(0), access=RegFieldAccessType.R))
+          RegField(1, b, RegFieldDescReserved())
         }})
     }
 
@@ -229,7 +231,8 @@ class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends
     }
 
     def thresholdRegDesc(i: Int) = RegFieldDesc(s"threshold_$i", s"Interrupt & claim threshold for target $i. Maximum value is ${nPriorities}.",
-      reset=if (nPriorities > 0) None else Some(1), access=RegFieldAccessType.RWSPECIAL)
+      reset=if (nPriorities > 0) None else Some(1),
+      wrType=Some(RegFieldWrType.MODIFY))
     def thresholdRegField(x: UInt, i: Int) = if (nPriorities > 0) RegField(32, x, thresholdRegDesc(i)) else RegField.r(32, x, thresholdRegDesc(i))
 
     val hartRegFields = Seq.tabulate(nHarts) { i =>
@@ -251,7 +254,9 @@ class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends
             s"Claim/Complete register for Target $i. Reading this register returns the claimed interrupt number and makes it no longer pending." +
             s"Writing the interrupt number back completes the interrupt.",
             reset = None,
-            access = RegFieldAccessType.RWSPECIAL))
+            wrType = Some(RegFieldWrType.MODIFY),
+            rdAction = Some(RegFieldRdAction.MODIFY),
+            volatile = true))
         )
       )
     } 

src/main/scala/rocket/BusErrorUnit.scala

@@ -57,24 +57,28 @@ class BusErrorUnit[T <: BusErrors](t: => T, params: BusErrorUnitParams)(implicit
       "cause", "Cause of error event", reset=Some(0.U(causeWidth.W)), enumerations=sources_enums.toMap)
 
     val (value, value_desc) = DescribedReg(UInt(width = sources.flatten.map(_.bits.getWidth).max),
-      "value", "Physical address of error event", reset=None)
+      "value", "Physical address of error event", reset=None, volatile=true)
     require(value.getWidth <= regWidth)
 
     val enable = Reg(init = Vec(sources.map(_.nonEmpty.B)))
     val enable_desc =  sources.zipWithIndex.map { case (s, i) =>
-      RegFieldDesc(s"enable_$i", "", reset=Some(if (s.nonEmpty) 1 else 0))}
+      if (s.nonEmpty) RegFieldDesc(s"enable_$i", "", reset=Some(1))
+      else RegFieldDescReserved()}
 
     val global_interrupt = Reg(init = Vec.fill(sources.size)(false.B))
     val global_interrupt_desc = sources.zipWithIndex.map { case (s, i) =>
-      RegFieldDesc(s"plic_interrupt_$i", "", reset=Some(0))}
+      if (s.nonEmpty) RegFieldDesc(s"plic_interrupt_$i", "", reset=Some(0))
+      else RegFieldDescReserved()}
 
     val accrued = Reg(init = Vec.fill(sources.size)(false.B))
     val accrued_desc = sources.zipWithIndex.map { case (s, i) =>
-      RegFieldDesc(s"accrued_$i", "", reset=Some(0))}
+      if (s.nonEmpty) RegFieldDesc(s"accrued_$i", "", reset=Some(0), volatile = true)
+      else RegFieldDescReserved()}
 
     val local_interrupt = Reg(init = Vec.fill(sources.size)(false.B))
     val local_interrupt_desc = sources.zipWithIndex.map { case (s, i) =>
-        RegFieldDesc(s"local_interrupt_$i", "", reset=Some(0))}
+      if (s.nonEmpty) RegFieldDesc(s"local_interrupt_$i", "", reset=Some(0))
+      else RegFieldDescReserved()}
 
     for ((((s, en), acc), i) <- (sources zip enable zip accrued).zipWithIndex; if s.nonEmpty) {
       when (s.get.valid) {