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RegFieldDesc: Update reg field descs to be more correct for devices.

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This commit is contained in:
Megan Wachs
2018-03-09 12:22:28 -08:00
parent 3063fd1b46
commit 7458378a4a
3 changed files with 28 additions and 17 deletions
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14
src/main/scala/rocket/BusErrorUnit.scala
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@ -57,24 +57,28 @@ class BusErrorUnit[T <: BusErrors](t: => T, params: BusErrorUnitParams)(implicit
"cause", "Cause of error event", reset=Some(0.U(causeWidth.W)), enumerations=sources_enums.toMap)
val (value, value_desc) = DescribedReg(UInt(width = sources.flatten.map(_.bits.getWidth).max),
"value", "Physical address of error event", reset=None)
"value", "Physical address of error event", reset=None, volatile=true)
require(value.getWidth <= regWidth)
val enable = Reg(init = Vec(sources.map(_.nonEmpty.B)))
val enable_desc = sources.zipWithIndex.map { case (s, i) =>
RegFieldDesc(s"enable_$i", "", reset=Some(if (s.nonEmpty) 1 else 0))}
if (s.nonEmpty) RegFieldDesc(s"enable_$i", "", reset=Some(1))
else RegFieldDescReserved()}
val global_interrupt = Reg(init = Vec.fill(sources.size)(false.B))
val global_interrupt_desc = sources.zipWithIndex.map { case (s, i) =>
RegFieldDesc(s"plic_interrupt_$i", "", reset=Some(0))}
if (s.nonEmpty) RegFieldDesc(s"plic_interrupt_$i", "", reset=Some(0))
else RegFieldDescReserved()}
val accrued = Reg(init = Vec.fill(sources.size)(false.B))
val accrued_desc = sources.zipWithIndex.map { case (s, i) =>
RegFieldDesc(s"accrued_$i", "", reset=Some(0))}
if (s.nonEmpty) RegFieldDesc(s"accrued_$i", "", reset=Some(0), volatile = true)
else RegFieldDescReserved()}
val local_interrupt = Reg(init = Vec.fill(sources.size)(false.B))
val local_interrupt_desc = sources.zipWithIndex.map { case (s, i) =>
RegFieldDesc(s"local_interrupt_$i", "", reset=Some(0))}
if (s.nonEmpty) RegFieldDesc(s"local_interrupt_$i", "", reset=Some(0))
else RegFieldDescReserved()}
for ((((s, en), acc), i) <- (sources zip enable zip accrued).zipWithIndex; if s.nonEmpty) {
when (s.get.valid) {