riscv/rocket-chip
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diplomacy: add reflection for parent modules to nodes

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This commit is contained in:
Wesley W. Terpstra
2017-10-19 18:51:00 -07:00
parent c4978712c9
commit 7453186b59
2 changed files with 9 additions and 0 deletions
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5
src/main/scala/diplomacy/LazyModule.scala
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@@ -17,6 +17,11 @@ abstract class LazyModule()(implicit val p: Parameters)
protected[diplomacy] var info: SourceInfo = UnlocatableSourceInfo protected[diplomacy] var info: SourceInfo = UnlocatableSourceInfo
protected[diplomacy] val parent = LazyModule.scope protected[diplomacy] val parent = LazyModule.scope
def parents: Seq[LazyModule] = parent match {
case None => Nil
case Some(x) => x +: x.parents
}
LazyModule.scope = Some(this) LazyModule.scope = Some(this)
parent.foreach(p => p.children = this :: p.children) parent.foreach(p => p.children = this :: p.children)

4
src/main/scala/diplomacy/Nodes.scala
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@@ -98,6 +98,8 @@ abstract class BaseNode(implicit val valName: ValName)
def omitGraphML = outputs.isEmpty && inputs.isEmpty def omitGraphML = outputs.isEmpty && inputs.isEmpty
lazy val nodedebugstring: String = "" lazy val nodedebugstring: String = ""
def parents: Seq[LazyModule] = lazyModule +: lazyModule.parents
def wirePrefix = { def wirePrefix = {
val camelCase = "([a-z])([A-Z])".r val camelCase = "([a-z])([A-Z])".r
val decamel = camelCase.replaceAllIn(valName.name, _ match { case camelCase(l, h) => l + "_" + h }) val decamel = camelCase.replaceAllIn(valName.name, _ match { case camelCase(l, h) => l + "_" + h })
@@ -129,6 +131,7 @@ case class NodeHandle[DI, UI, BI <: Data, DO, UO, BO <: Data]
trait InwardNodeHandle[DI, UI, BI <: Data] trait InwardNodeHandle[DI, UI, BI <: Data]
{ {
protected[diplomacy] val inward: InwardNode[DI, UI, BI] protected[diplomacy] val inward: InwardNode[DI, UI, BI]
def parentsIn: Seq[LazyModule] = inward.parents
def := (h: OutwardNodeHandle[DI, UI, BI])(implicit p: Parameters, sourceInfo: SourceInfo) { inward.:=(h)(p, sourceInfo) } def := (h: OutwardNodeHandle[DI, UI, BI])(implicit p: Parameters, sourceInfo: SourceInfo) { inward.:=(h)(p, sourceInfo) }
def :*= (h: OutwardNodeHandle[DI, UI, BI])(implicit p: Parameters, sourceInfo: SourceInfo) { inward.:*=(h)(p, sourceInfo) } def :*= (h: OutwardNodeHandle[DI, UI, BI])(implicit p: Parameters, sourceInfo: SourceInfo) { inward.:*=(h)(p, sourceInfo) }
def :=* (h: OutwardNodeHandle[DI, UI, BI])(implicit p: Parameters, sourceInfo: SourceInfo) { inward.:=*(h)(p, sourceInfo) } def :=* (h: OutwardNodeHandle[DI, UI, BI])(implicit p: Parameters, sourceInfo: SourceInfo) { inward.:=*(h)(p, sourceInfo) }
@@ -170,6 +173,7 @@ trait InwardNode[DI, UI, BI <: Data] extends BaseNode with InwardNodeHandle[DI,
trait OutwardNodeHandle[DO, UO, BO <: Data] trait OutwardNodeHandle[DO, UO, BO <: Data]
{ {
protected[diplomacy] val outward: OutwardNode[DO, UO, BO] protected[diplomacy] val outward: OutwardNode[DO, UO, BO]
def parentsOut: Seq[LazyModule] = outward.parents
} }
trait OutwardNode[DO, UO, BO <: Data] extends BaseNode with OutwardNodeHandle[DO, UO, BO] trait OutwardNode[DO, UO, BO <: Data] extends BaseNode with OutwardNodeHandle[DO, UO, BO]