riscv/rocket-chip
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Cut imem.resp.ready critical path with a flow queue

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This is only necessary for RVC, where the decode latency is much higher.
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Andrew Waterman 2017-04-02 22:25:13 -07:00 committed by Andrew Waterman
parent 3e72f9779f
commit 744fb2e4b9
1 changed files with 2 additions and 1 deletions
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3
src/main/scala/rocket/Rocket.scala
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@ -4,6 +4,7 @@
package rocket package rocket
import Chisel._ import Chisel._
import chisel3.core.withReset
import config._ import config._
import tile._ import tile._
import uncore.constants._ import uncore.constants._
@ -172,7 +173,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
val ibuf = Module(new IBuf) val ibuf = Module(new IBuf)
val id_expanded_inst = ibuf.io.inst.map(_.bits.inst) val id_expanded_inst = ibuf.io.inst.map(_.bits.inst)
val id_inst = id_expanded_inst.map(_.bits) val id_inst = id_expanded_inst.map(_.bits)
ibuf.io.imem <> io.imem.resp ibuf.io.imem <> (if (usingCompressed) withReset(reset || take_pc) { Queue(io.imem.resp, 1, flow = true) } else io.imem.resp)
ibuf.io.kill := take_pc ibuf.io.kill := take_pc
require(decodeWidth == 1 /* TODO */ && retireWidth == decodeWidth) require(decodeWidth == 1 /* TODO */ && retireWidth == decodeWidth)