riscv/rocket-chip
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Make TLB report when it's safe to prefetch within a page

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This commit is contained in:
Andrew Waterman 2017-08-02 17:09:38 -07:00
parent d9821a74ce
commit 744cdb2f72
1 changed files with 4 additions and 0 deletions
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src/main/scala/rocket/TLB.scala
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@ -49,6 +49,7 @@ class TLBResp(implicit p: Parameters) extends CoreBundle()(p) {
val ae = new TLBExceptions val ae = new TLBExceptions
val ma = new TLBExceptions val ma = new TLBExceptions
val cacheable = Bool() val cacheable = Bool()
val prefetchable = Bool()
} }
class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) {
@ -113,6 +114,7 @@ class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters
def fastCheck(member: TLManagerParameters => Boolean) = def fastCheck(member: TLManagerParameters => Boolean) =
legal_address && edge.manager.fastProperty(mpu_physaddr, member, (b:Boolean) => Bool(b)) legal_address && edge.manager.fastProperty(mpu_physaddr, member, (b:Boolean) => Bool(b))
val cacheable = fastCheck(_.supportsAcquireB) val cacheable = fastCheck(_.supportsAcquireB)
val homogeneous = TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << pgIdxBits)(mpu_physaddr).homogeneous
val prot_r = fastCheck(_.supportsGet) && pmp.io.r val prot_r = fastCheck(_.supportsGet) && pmp.io.r
val prot_w = fastCheck(_.supportsPutFull) && pmp.io.w val prot_w = fastCheck(_.supportsPutFull) && pmp.io.w
val prot_al = fastCheck(_.supportsLogical) || cacheable val prot_al = fastCheck(_.supportsLogical) || cacheable
@ -181,6 +183,7 @@ class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters
val pal_array = Cat(Fill(2, prot_al), entries.init.map(_.pal).asUInt) val pal_array = Cat(Fill(2, prot_al), entries.init.map(_.pal).asUInt)
val eff_array = Cat(Fill(2, prot_eff), entries.init.map(_.eff).asUInt) val eff_array = Cat(Fill(2, prot_eff), entries.init.map(_.eff).asUInt)
val c_array = Cat(Fill(2, cacheable), entries.init.map(_.c).asUInt) val c_array = Cat(Fill(2, cacheable), entries.init.map(_.c).asUInt)
val prefetchable_array = Cat(cacheable && homogeneous, false.B, entries.init.map(_.c).asUInt)
val misaligned = (io.req.bits.vaddr & (UIntToOH(io.req.bits.size) - 1)).orR val misaligned = (io.req.bits.vaddr & (UIntToOH(io.req.bits.size) - 1)).orR
val bad_va = vm_enabled && val bad_va = vm_enabled &&
@ -226,6 +229,7 @@ class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters
io.resp.ma.st := (ma_st_array & hits).orR io.resp.ma.st := (ma_st_array & hits).orR
io.resp.ma.inst := false // this is up to the pipeline to figure out io.resp.ma.inst := false // this is up to the pipeline to figure out
io.resp.cacheable := (c_array & hits).orR io.resp.cacheable := (c_array & hits).orR
io.resp.prefetchable := (prefetchable_array & hits).orR && edge.manager.managers.forall(m => !m.supportsAcquireB || m.supportsHint)
io.resp.miss := do_refill || tlb_miss || multipleHits io.resp.miss := do_refill || tlb_miss || multipleHits
io.resp.paddr := Cat(ppn, pgOffset) io.resp.paddr := Cat(ppn, pgOffset)