riscv/rocket-chip
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Rename some params, use refactored TileLink

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This commit is contained in:
Henry Cook
2015-02-01 20:04:13 -08:00
parent 00e074cdd9
commit 741e6b77ad
12 changed files with 248 additions and 300 deletions
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28
rocket/src/main/scala/ptw.scala
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@ -6,28 +6,28 @@ import Chisel._
import uncore._
import Util._
class PTWResp extends Bundle {
class PTWResp extends CoreBundle {
val error = Bool()
val ppn = UInt(width = params(PPNBits))
val perm = Bits(width = params(PermBits))
val ppn = UInt(width = ppnBits)
val perm = Bits(width = permBits)
}
class TLBPTWIO extends Bundle {
val req = Decoupled(UInt(width = params(VPNBits)))
class TLBPTWIO extends CoreBundle {
val req = Decoupled(UInt(width = vpnBits))
val resp = Valid(new PTWResp).flip
val status = new Status().asInput
val invalidate = Bool(INPUT)
val sret = Bool(INPUT)
}
class DatapathPTWIO extends Bundle {
val ptbr = UInt(INPUT, params(PAddrBits))
class DatapathPTWIO extends CoreBundle {
val ptbr = UInt(INPUT, paddrBits)
val invalidate = Bool(INPUT)
val sret = Bool(INPUT)
val status = new Status().asInput
}
class PTW(n: Int) extends Module
class PTW(n: Int) extends CoreModule
{
val io = new Bundle {
val requestor = Vec.fill(n){new TLBPTWIO}.flip
@ -36,8 +36,8 @@ class PTW(n: Int) extends Module
}
val levels = 3
val bitsPerLevel = params(VPNBits)/levels
require(params(VPNBits) == levels * bitsPerLevel)
val bitsPerLevel = vpnBits/levels
require(vpnBits == levels * bitsPerLevel)
val s_ready :: s_req :: s_wait :: s_done :: s_error :: Nil = Enum(UInt(), 5)
val state = Reg(init=s_ready)
@ -49,14 +49,14 @@ class PTW(n: Int) extends Module
val vpn_idx = Vec((0 until levels).map(i => (r_req_vpn >> (levels-i-1)*bitsPerLevel)(bitsPerLevel-1,0)))(count)
val arb = Module(new RRArbiter(UInt(width = params(VPNBits)), n))
val arb = Module(new RRArbiter(UInt(width = vpnBits), n))
arb.io.in <> io.requestor.map(_.req)
arb.io.out.ready := state === s_ready
when (arb.io.out.fire()) {
r_req_vpn := arb.io.out.bits
r_req_dest := arb.io.chosen
r_pte := Cat(io.dpath.ptbr(params(PAddrBits)-1,params(PgIdxBits)), io.mem.resp.bits.data(params(PgIdxBits)-1,0))
r_pte := Cat(io.dpath.ptbr(paddrBits-1,pgIdxBits), io.mem.resp.bits.data(pgIdxBits-1,0))
}
when (io.mem.resp.valid) {
@ -67,13 +67,13 @@ class PTW(n: Int) extends Module
io.mem.req.bits.phys := Bool(true)
io.mem.req.bits.cmd := M_XRD
io.mem.req.bits.typ := MT_D
io.mem.req.bits.addr := Cat(r_pte(params(PAddrBits)-1,params(PgIdxBits)), vpn_idx).toUInt << log2Up(params(XprLen)/8)
io.mem.req.bits.addr := Cat(r_pte(paddrBits-1,pgIdxBits), vpn_idx).toUInt << log2Up(xLen/8)
io.mem.req.bits.kill := Bool(false)
val resp_val = state === s_done || state === s_error
val resp_err = state === s_error || state === s_wait
val r_resp_ppn = io.mem.req.bits.addr >> UInt(params(PgIdxBits))
val r_resp_ppn = io.mem.req.bits.addr >> UInt(pgIdxBits)
val resp_ppn = Vec((0 until levels-1).map(i => Cat(r_resp_ppn >> bitsPerLevel*(levels-i-1), r_req_vpn(bitsPerLevel*(levels-i-1)-1,0))) :+ r_resp_ppn)(count)
for (i <- 0 until io.requestor.size) {