Rename some params, use refactored TileLink
This commit is contained in:
Henry Cook
@ -6,17 +6,21 @@ import Chisel._
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import uncore._
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import Util._
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case object WordBits extends Field[Int]
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case object StoreDataQueueDepth extends Field[Int]
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case object ReplayQueueDepth extends Field[Int]
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case object NMSHRs extends Field[Int]
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case object LRSCCycles extends Field[Int]
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case object NDTLBEntries extends Field[Int]
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abstract trait L1HellaCacheParameters extends L1CacheParameters {
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val wordBits = params(WordBits)
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val wordBytes = wordBits/8
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val wordOffBits = log2Up(wordBytes)
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val idxMSB = untagBits-1
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val idxLSB = blockOffBits
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val offsetmsb = idxLSB-1
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val offsetlsb = wordOffBits
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val rowWords = rowBits/wordBits
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val doNarrowRead = coreDataBits * nWays % rowBits == 0
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val encDataBits = code.width(coreDataBits)
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val encRowBits = encDataBits*rowWords
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@ -27,64 +31,39 @@ abstract trait L1HellaCacheParameters extends L1CacheParameters {
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abstract class L1HellaCacheBundle extends Bundle with L1HellaCacheParameters
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abstract class L1HellaCacheModule extends Module with L1HellaCacheParameters
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class StoreGen(typ: Bits, addr: Bits, dat: Bits)
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{
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val byte = typ === MT_B || typ === MT_BU
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val half = typ === MT_H || typ === MT_HU
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val word = typ === MT_W || typ === MT_WU
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def mask =
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Mux(byte, Bits( 1) << addr(2,0),
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Mux(half, Bits( 3) << Cat(addr(2,1), Bits(0,1)),
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Mux(word, Bits( 15) << Cat(addr(2), Bits(0,2)),
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Bits(255))))
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def data =
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Mux(byte, Fill(8, dat( 7,0)),
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Mux(half, Fill(4, dat(15,0)),
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wordData))
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lazy val wordData =
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Mux(word, Fill(2, dat(31,0)),
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dat)
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}
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class LoadGen(typ: Bits, addr: Bits, dat: Bits, zero: Bool)
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{
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val t = new StoreGen(typ, addr, dat)
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val sign = typ === MT_B || typ === MT_H || typ === MT_W || typ === MT_D
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val wordShift = Mux(addr(2), dat(63,32), dat(31,0))
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val word = Cat(Mux(t.word, Fill(32, sign && wordShift(31)), dat(63,32)), wordShift)
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val halfShift = Mux(addr(1), word(31,16), word(15,0))
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val half = Cat(Mux(t.half, Fill(48, sign && halfShift(15)), word(63,16)), halfShift)
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val byteShift = Mux(zero, UInt(0), Mux(addr(0), half(15,8), half(7,0)))
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val byte = Cat(Mux(zero || t.byte, Fill(56, sign && byteShift(7)), half(63,8)), byteShift)
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trait HasCoreMemOp extends CoreBundle {
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val addr = UInt(width = coreMaxAddrBits)
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val tag = Bits(width = coreDCacheReqTagBits)
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val cmd = Bits(width = M_SZ)
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val typ = Bits(width = MT_SZ)
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}
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trait HasCoreData extends CoreBundle {
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val data = Bits(width = coreDataBits)
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}
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class HellaCacheReqInternal extends CoreBundle {
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val kill = Bool()
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val typ = Bits(width = MT_SZ)
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val phys = Bool()
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val addr = UInt(width = coreMaxAddrBits)
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val tag = Bits(width = coreDCacheReqTagBits)
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val cmd = Bits(width = M_SZ)
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trait HasSDQId extends CoreBundle with L1HellaCacheParameters {
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val sdq_id = UInt(width = log2Up(sdqDepth))
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}
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class HellaCacheReq extends HellaCacheReqInternal
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with HasCoreData
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trait HasMissInfo extends CoreBundle with L1HellaCacheParameters {
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val tag_match = Bool()
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val old_meta = new L1Metadata
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val way_en = Bits(width = nWays)
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}
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class HellaCacheResp extends CoreBundle
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with HasCoreData {
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class HellaCacheReqInternal extends HasCoreMemOp {
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val kill = Bool()
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val phys = Bool()
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}
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class HellaCacheReq extends HellaCacheReqInternal with HasCoreData
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class HellaCacheResp extends HasCoreMemOp with HasCoreData {
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val nack = Bool() // comes 2 cycles after req.fire
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val replay = Bool()
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val typ = Bits(width = 3)
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val has_data = Bool()
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val data_subword = Bits(width = coreDataBits)
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val tag = Bits(width = coreDCacheReqTagBits)
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val cmd = Bits(width = 4)
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val addr = UInt(width = coreMaxAddrBits)
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val store_data = Bits(width = coreDataBits)
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}
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@ -108,27 +87,12 @@ class HellaCacheIO extends CoreBundle {
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val ordered = Bool(INPUT)
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}
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trait HasSDQId extends CoreBundle with L1HellaCacheParameters {
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val sdq_id = UInt(width = log2Up(sdqDepth))
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}
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trait HasMissInfo extends CoreBundle with L1HellaCacheParameters {
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val tag_match = Bool()
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val old_meta = new L1Metadata
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val way_en = Bits(width = nWays)
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}
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class Replay extends HellaCacheReqInternal with HasCoreData
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class ReplayInternal extends HellaCacheReqInternal with HasSDQId
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class MSHRReq extends Replay with HasMissInfo
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class MSHRReqInternal extends ReplayInternal with HasMissInfo
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class DataReadReq extends L1HellaCacheBundle {
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class L1DataReadReq extends L1HellaCacheBundle {
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val way_en = Bits(width = nWays)
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val addr = Bits(width = untagBits)
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}
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class DataWriteReq extends DataReadReq {
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class L1DataWriteReq extends L1DataReadReq {
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val wmask = Bits(width = rowWords)
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val data = Bits(width = encRowBits)
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}
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@ -152,14 +116,16 @@ class L1Metadata extends Metadata with L1HellaCacheParameters {
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val coh = co.clientMetadataOnFlush.clone
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}
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class InternalProbe extends Probe with HasClientTransactionId
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class Replay extends HellaCacheReqInternal with HasCoreData
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class ReplayInternal extends HellaCacheReqInternal with HasSDQId
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class WritebackReq extends L1HellaCacheBundle {
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val tag = Bits(width = tagBits)
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val idx = Bits(width = idxBits)
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class MSHRReq extends Replay with HasMissInfo
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class MSHRReqInternal extends ReplayInternal with HasMissInfo
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class ProbeInternal extends Probe with HasClientTransactionId
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class WritebackReq extends Release with CacheParameters {
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val way_en = Bits(width = nWays)
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val client_xact_id = Bits(width = params(TLClientXactIdBits))
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val r_type = UInt(width = co.releaseTypeWidth)
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}
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class MSHR(id: Int) extends L1HellaCacheModule {
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@ -174,7 +140,7 @@ class MSHR(id: Int) extends L1HellaCacheModule {
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val tag = Bits(OUTPUT, tagBits)
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val mem_req = Decoupled(new Acquire)
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val mem_resp = new DataWriteReq().asOutput
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val mem_resp = new L1DataWriteReq().asOutput
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val meta_read = Decoupled(new L1MetaReadReq)
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val meta_write = Decoupled(new L1MetaWriteReq)
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val replay = Decoupled(new ReplayInternal)
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@ -188,17 +154,19 @@ class MSHR(id: Int) extends L1HellaCacheModule {
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val state = Reg(init=s_invalid)
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val acquire_type = Reg(UInt())
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val release_type = Reg(UInt())
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val line_state = Reg(new ClientMetadata)
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val req = Reg(new MSHRReqInternal())
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val req_cmd = io.req_bits.cmd
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val req_idx = req.addr(untagBits-1,blockOffBits)
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val idx_match = req_idx === io.req_bits.addr(untagBits-1,blockOffBits)
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val sec_rdy = idx_match && (state === s_wb_req || state === s_wb_resp || state === s_meta_clear || (state === s_refill_req || state === s_refill_resp) && !co.needsTransactionOnSecondaryMiss(req_cmd, io.mem_req.bits))
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val sec_rdy = idx_match && !co.needsTransactionOnSecondaryMiss(req_cmd, io.mem_req.bits) &&
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Vec(s_wb_req, s_wb_resp, s_meta_clear, s_refill_req, s_refill_resp).contains(state)
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val reply = io.mem_grant.valid && io.mem_grant.bits.payload.client_xact_id === UInt(id)
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val (refill_cnt, refill_done) = Counter(reply && co.messageUpdatesDataArray(io.mem_grant.bits.payload), refillCycles) // TODO: Zero width?
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val gnt_multi_data = io.mem_grant.bits.payload.hasMultibeatData()
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val (refill_cnt, refill_count_done) = Counter(reply && gnt_multi_data, refillCycles) // TODO: Zero width?
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val refill_done = reply && (!gnt_multi_data || refill_count_done)
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val wb_done = reply && (state === s_wb_resp)
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val meta_on_flush = co.clientMetadataOnFlush
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@ -234,16 +202,14 @@ class MSHR(id: Int) extends L1HellaCacheModule {
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state := s_meta_clear
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}
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when (io.wb_req.fire()) { // s_wb_req
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state := s_wb_resp
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state := Mux(io.wb_req.bits.requiresAck(), s_wb_resp, s_meta_clear)
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}
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when (io.req_sec_val && io.req_sec_rdy) { // s_wb_req, s_wb_resp, s_refill_req
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acquire_type := co.getAcquireTypeOnSecondaryMiss(req_cmd, meta_on_flush, io.mem_req.bits)
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}
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when (io.req_pri_val && io.req_pri_rdy) {
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line_state := meta_on_flush
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refill_cnt := UInt(0)
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acquire_type := co.getAcquireTypeOnPrimaryMiss(req_cmd, meta_on_flush)
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release_type := co.getReleaseTypeOnVoluntaryWriteback() //TODO downgrades etc
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req := io.req_bits
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when (io.req_bits.tag_match) {
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@ -259,8 +225,8 @@ class MSHR(id: Int) extends L1HellaCacheModule {
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}
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val ackq = Module(new Queue(new LogicalNetworkIO(new Finish), 1))
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ackq.io.enq.valid := (wb_done || refill_done) && co.requiresAckForGrant(io.mem_grant.bits.payload)
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ackq.io.enq.bits.payload.manager_xact_id := io.mem_grant.bits.payload.manager_xact_id
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ackq.io.enq.valid := (wb_done || refill_done) && io.mem_grant.bits.payload.requiresAck()
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ackq.io.enq.bits.payload := io.mem_grant.bits.payload.makeFinish()
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ackq.io.enq.bits.header.dst := io.mem_grant.bits.header.src
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val can_finish = state === s_invalid || state === s_refill_req || state === s_refill_resp
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io.mem_finish.valid := ackq.io.deq.valid && can_finish
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@ -286,14 +252,17 @@ class MSHR(id: Int) extends L1HellaCacheModule {
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io.meta_write.bits.way_en := req.way_en
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io.wb_req.valid := state === s_wb_req && ackq.io.enq.ready
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io.wb_req.bits.tag := req.old_meta.tag
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io.wb_req.bits.idx := req_idx
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io.wb_req.bits := Release.makeVoluntaryWriteback(
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meta = req.old_meta.coh,
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client_xact_id = UInt(id),
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addr_block = Cat(req.old_meta.tag, req_idx))
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io.wb_req.bits.way_en := req.way_en
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io.wb_req.bits.client_xact_id := Bits(id)
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io.wb_req.bits.r_type := co.getReleaseTypeOnVoluntaryWriteback()
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io.mem_req.valid := state === s_refill_req && ackq.io.enq.ready
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io.mem_req.bits := Acquire(acquire_type, Cat(io.tag, req_idx).toUInt, Bits(id))
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io.mem_req.bits := Acquire(
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a_type = acquire_type,
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addr_block = Cat(io.tag, req_idx).toUInt,
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client_xact_id = Bits(id))
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io.mem_finish <> ackq.io.deq
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io.meta_read.valid := state === s_drain_rpq
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@ -317,7 +286,7 @@ class MSHRFile extends L1HellaCacheModule {
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val secondary_miss = Bool(OUTPUT)
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val mem_req = Decoupled(new Acquire)
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val mem_resp = new DataWriteReq().asOutput
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val mem_resp = new L1DataWriteReq().asOutput
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val meta_read = Decoupled(new L1MetaReadReq)
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val meta_write = Decoupled(new L1MetaWriteReq)
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val replay = Decoupled(new Replay)
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@ -341,10 +310,14 @@ class MSHRFile extends L1HellaCacheModule {
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val tag_match = Mux1H(idxMatch, tagList) === io.req.bits.addr >> untagBits
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val wbTagList = Vec.fill(nMSHRs){Bits()}
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val memRespMux = Vec.fill(nMSHRs){new DataWriteReq}
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val memRespMux = Vec.fill(nMSHRs){new L1DataWriteReq}
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val meta_read_arb = Module(new Arbiter(new L1MetaReadReq, nMSHRs))
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val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq, nMSHRs))
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val mem_req_arb = Module(new LockingArbiter(new Acquire, nMSHRs, outerDataBeats, co.messageHasData _))
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val mem_req_arb = Module(new LockingArbiter(
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new Acquire,
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nMSHRs,
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outerDataBeats,
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(a: Acquire) => a.hasMultibeatData()))
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val mem_finish_arb = Module(new Arbiter(new LogicalNetworkIO(new Finish), nMSHRs))
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val wb_req_arb = Module(new Arbiter(new WritebackReq, nMSHRs))
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val replay_arb = Module(new Arbiter(new ReplayInternal, nMSHRs))
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@ -362,7 +335,7 @@ class MSHRFile extends L1HellaCacheModule {
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idxMatch(i) := mshr.io.idx_match
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tagList(i) := mshr.io.tag
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wbTagList(i) := mshr.io.wb_req.bits.tag
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wbTagList(i) := mshr.io.wb_req.bits.addr_block >> UInt(idxBits)
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alloc_arb.io.in(i).valid := mshr.io.req_pri_rdy
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mshr.io.req_pri_val := alloc_arb.io.in(i).ready
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@ -413,9 +386,9 @@ class MSHRFile extends L1HellaCacheModule {
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class WritebackUnit extends L1HellaCacheModule {
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val io = new Bundle {
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val req = Decoupled(new WritebackReq()).flip
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val req = Decoupled(new WritebackReq).flip
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val meta_read = Decoupled(new L1MetaReadReq)
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val data_req = Decoupled(new DataReadReq())
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val data_req = Decoupled(new L1DataReadReq)
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val data_resp = Bits(INPUT, encRowBits)
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val release = Decoupled(new Release)
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}
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@ -423,9 +396,10 @@ class WritebackUnit extends L1HellaCacheModule {
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val active = Reg(init=Bool(false))
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val r1_data_req_fired = Reg(init=Bool(false))
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val r2_data_req_fired = Reg(init=Bool(false))
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val cnt = Reg(init = UInt(0, width = log2Up(refillCycles+1))) //TODO Zero width
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val data_req_cnt = Reg(init = UInt(0, width = log2Up(refillCycles+1))) //TODO Zero width
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val buf_v = (if(refillCyclesPerBeat > 1) Reg(init=Bits(0, width = refillCyclesPerBeat-1)) else Bits(1))
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val beat_done = buf_v.andR
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val (beat_cnt, all_beats_done) = Counter(io.release.fire(), outerDataBeats)
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val req = Reg(new WritebackReq)
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io.release.valid := false
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@ -434,59 +408,62 @@ class WritebackUnit extends L1HellaCacheModule {
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r2_data_req_fired := r1_data_req_fired
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when (io.data_req.fire() && io.meta_read.fire()) {
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r1_data_req_fired := true
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cnt := cnt + 1
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data_req_cnt := data_req_cnt + 1
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}
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when (r2_data_req_fired) {
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io.release.valid := beat_done
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when(!io.release.ready) {
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r1_data_req_fired := false
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r2_data_req_fired := false
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cnt := cnt - Mux[UInt](Bool(refillCycles > 1) && r1_data_req_fired, 2, 1)
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data_req_cnt := data_req_cnt - Mux[UInt](Bool(refillCycles > 1) && r1_data_req_fired, 2, 1)
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} .elsewhen(beat_done) { if(refillCyclesPerBeat > 1) buf_v := 0 }
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when(!r1_data_req_fired) {
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active := cnt < UInt(refillCycles)
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active := data_req_cnt < UInt(refillCycles)
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}
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}
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}
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when (io.req.fire()) {
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active := true
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cnt := 0
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data_req_cnt := 0
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if(refillCyclesPerBeat > 1) buf_v := 0
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req := io.req.bits
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}
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val fire = active && cnt < UInt(refillCycles)
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io.req.ready := !active
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// We reissue the meta read as it sets up the muxing for s2_data_muxed
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val req_idx = req.addr_block(idxBits-1, 0)
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val fire = active && data_req_cnt < UInt(refillCycles)
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// We reissue the meta read as it sets up the mux ctrl for s2_data_muxed
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io.meta_read.valid := fire
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io.meta_read.bits.idx := req.idx
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io.meta_read.bits.tag := req.tag
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io.meta_read.bits.idx := req_idx
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io.meta_read.bits.tag := req.addr_block >> UInt(idxBits)
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io.data_req.valid := fire
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io.data_req.bits.way_en := req.way_en
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io.data_req.bits.addr := (if(refillCycles > 1) Cat(req.idx, cnt(log2Up(refillCycles)-1,0))
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else req.idx) << rowOffBits
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io.data_req.bits.addr := (if(refillCycles > 1)
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Cat(req_idx, data_req_cnt(log2Up(refillCycles)-1,0))
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else req_idx) << rowOffBits
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io.release.bits.r_type := req.r_type
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io.release.bits.addr := Cat(req.tag, req.idx).toUInt
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io.release.bits.client_xact_id := req.client_xact_id
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io.release.bits.data :=
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(if(refillCyclesPerBeat > 1) {
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val data_buf = Reg(Bits())
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when(active && r2_data_req_fired && !beat_done) {
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data_buf := Cat(io.data_resp, data_buf((refillCyclesPerBeat-1)*encRowBits-1, encRowBits))
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buf_v := (if(refillCyclesPerBeat > 2)
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Cat(UInt(1), buf_v(refillCyclesPerBeat-2,1))
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else UInt(1))
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}
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Cat(io.data_resp, data_buf)
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} else { io.data_resp })
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io.release.bits := req
|
||||
io.release.bits.addr_beat := beat_cnt
|
||||
io.release.bits.data := (if(refillCyclesPerBeat > 1) {
|
||||
// If the cache rows are narrower than a TLDataBeat,
|
||||
// then buffer enough data_resps to make a whole beat
|
||||
val data_buf = Reg(Bits())
|
||||
when(active && r2_data_req_fired && !beat_done) {
|
||||
data_buf := Cat(io.data_resp, data_buf((refillCyclesPerBeat-1)*encRowBits-1, encRowBits))
|
||||
buf_v := (if(refillCyclesPerBeat > 2)
|
||||
Cat(UInt(1), buf_v(refillCyclesPerBeat-2,1))
|
||||
else UInt(1))
|
||||
}
|
||||
Cat(io.data_resp, data_buf)
|
||||
} else { io.data_resp })
|
||||
}
|
||||
|
||||
class ProbeUnit extends L1HellaCacheModule {
|
||||
val io = new Bundle {
|
||||
val req = Decoupled(new InternalProbe).flip
|
||||
val req = Decoupled(new ProbeInternal).flip
|
||||
val rep = Decoupled(new Release)
|
||||
val meta_read = Decoupled(new L1MetaReadReq)
|
||||
val meta_write = Decoupled(new L1MetaWriteReq)
|
||||
@ -500,7 +477,7 @@ class ProbeUnit extends L1HellaCacheModule {
|
||||
val state = Reg(init=s_invalid)
|
||||
val line_state = Reg(co.clientMetadataOnFlush.clone)
|
||||
val way_en = Reg(Bits())
|
||||
val req = Reg(new InternalProbe)
|
||||
val req = Reg(new ProbeInternal)
|
||||
val hit = way_en.orR
|
||||
|
||||
when (state === s_meta_write && io.meta_write.ready) {
|
||||
@ -538,36 +515,32 @@ class ProbeUnit extends L1HellaCacheModule {
|
||||
state := s_invalid
|
||||
}
|
||||
|
||||
val reply = Mux(hit, req.makeRelease(req.client_xact_id, line_state),
|
||||
req.makeRelease(req.client_xact_id))
|
||||
io.req.ready := state === s_invalid
|
||||
io.rep.valid := state === s_release &&
|
||||
!(hit && co.needsWriteback(line_state)) // Otherwise WBU will issue release
|
||||
io.rep.bits := Release(co.getReleaseTypeOnProbe(req,
|
||||
Mux(hit, line_state, co.clientMetadataOnFlush)),
|
||||
req.addr,
|
||||
req.client_xact_id)
|
||||
io.rep.bits := reply
|
||||
|
||||
io.meta_read.valid := state === s_meta_read
|
||||
io.meta_read.bits.idx := req.addr
|
||||
io.meta_read.bits.tag := req.addr >> idxBits
|
||||
io.meta_read.bits.idx := req.addr_block
|
||||
io.meta_read.bits.tag := req.addr_block >> idxBits
|
||||
|
||||
io.meta_write.valid := state === s_meta_write
|
||||
io.meta_write.bits.way_en := way_en
|
||||
io.meta_write.bits.idx := req.addr
|
||||
io.meta_write.bits.idx := req.addr_block
|
||||
io.meta_write.bits.data.tag := req.addr_block >> idxBits
|
||||
io.meta_write.bits.data.coh := co.clientMetadataOnProbe(req, line_state)
|
||||
io.meta_write.bits.data.tag := req.addr >> UInt(idxBits)
|
||||
|
||||
io.wb_req.valid := state === s_writeback_req
|
||||
io.wb_req.bits := reply
|
||||
io.wb_req.bits.way_en := way_en
|
||||
io.wb_req.bits.idx := req.addr
|
||||
io.wb_req.bits.tag := req.addr >> UInt(idxBits)
|
||||
io.wb_req.bits.r_type := co.getReleaseTypeOnProbe(req, Mux(hit, line_state, co.clientMetadataOnFlush))
|
||||
io.wb_req.bits.client_xact_id := req.client_xact_id
|
||||
}
|
||||
|
||||
class DataArray extends L1HellaCacheModule {
|
||||
val io = new Bundle {
|
||||
val read = Decoupled(new DataReadReq).flip
|
||||
val write = Decoupled(new DataWriteReq).flip
|
||||
val read = Decoupled(new L1DataReadReq).flip
|
||||
val write = Decoupled(new L1DataWriteReq).flip
|
||||
val resp = Vec.fill(nWays){Bits(OUTPUT, encRowBits)}
|
||||
}
|
||||
|
||||
@ -612,47 +585,6 @@ class DataArray extends L1HellaCacheModule {
|
||||
io.write.ready := Bool(true)
|
||||
}
|
||||
|
||||
class AMOALU extends L1HellaCacheModule {
|
||||
val io = new Bundle {
|
||||
val addr = Bits(INPUT, blockOffBits)
|
||||
val cmd = Bits(INPUT, 4)
|
||||
val typ = Bits(INPUT, 3)
|
||||
val lhs = Bits(INPUT, coreDataBits)
|
||||
val rhs = Bits(INPUT, coreDataBits)
|
||||
val out = Bits(OUTPUT, coreDataBits)
|
||||
}
|
||||
|
||||
require(coreDataBits == 64)
|
||||
val storegen = new StoreGen(io.typ, io.addr, io.rhs)
|
||||
val rhs = storegen.wordData
|
||||
|
||||
val sgned = io.cmd === M_XA_MIN || io.cmd === M_XA_MAX
|
||||
val max = io.cmd === M_XA_MAX || io.cmd === M_XA_MAXU
|
||||
val min = io.cmd === M_XA_MIN || io.cmd === M_XA_MINU
|
||||
val word = io.typ === MT_W || io.typ === MT_WU || io.typ === MT_B || io.typ === MT_BU
|
||||
|
||||
val mask = SInt(-1,64) ^ (io.addr(2) << 31)
|
||||
val adder_out = (io.lhs & mask).toUInt + (rhs & mask)
|
||||
|
||||
val cmp_lhs = Mux(word && !io.addr(2), io.lhs(31), io.lhs(63))
|
||||
val cmp_rhs = Mux(word && !io.addr(2), rhs(31), rhs(63))
|
||||
val lt_lo = io.lhs(31,0) < rhs(31,0)
|
||||
val lt_hi = io.lhs(63,32) < rhs(63,32)
|
||||
val eq_hi = io.lhs(63,32) === rhs(63,32)
|
||||
val lt = Mux(word, Mux(io.addr(2), lt_hi, lt_lo), lt_hi || eq_hi && lt_lo)
|
||||
val less = Mux(cmp_lhs === cmp_rhs, lt, Mux(sgned, cmp_lhs, cmp_rhs))
|
||||
|
||||
val out = Mux(io.cmd === M_XA_ADD, adder_out,
|
||||
Mux(io.cmd === M_XA_AND, io.lhs & rhs,
|
||||
Mux(io.cmd === M_XA_OR, io.lhs | rhs,
|
||||
Mux(io.cmd === M_XA_XOR, io.lhs ^ rhs,
|
||||
Mux(Mux(less, min, max), io.lhs,
|
||||
storegen.data)))))
|
||||
|
||||
val wmask = FillInterleaved(8, storegen.mask)
|
||||
io.out := wmask & out | ~wmask & io.lhs
|
||||
}
|
||||
|
||||
class HellaCache extends L1HellaCacheModule {
|
||||
val io = new Bundle {
|
||||
val cpu = (new HellaCacheIO).flip
|
||||
@ -693,7 +625,7 @@ class HellaCache extends L1HellaCacheModule {
|
||||
val s1_sc = s1_req.cmd === M_XSC
|
||||
val s1_readwrite = s1_read || s1_write || isPrefetch(s1_req.cmd)
|
||||
|
||||
val dtlb = Module(new TLB(params(NDTLBEntries)))
|
||||
val dtlb = Module(new TLB)
|
||||
dtlb.io.ptw <> io.cpu.ptw
|
||||
dtlb.io.req.valid := s1_valid_masked && s1_readwrite && !s1_req.phys
|
||||
dtlb.io.req.bits.passthrough := s1_req.phys
|
||||
@ -754,8 +686,8 @@ class HellaCache extends L1HellaCacheModule {
|
||||
|
||||
// data
|
||||
val data = Module(new DataArray)
|
||||
val readArb = Module(new Arbiter(new DataReadReq, 4))
|
||||
val writeArb = Module(new Arbiter(new DataWriteReq, 2))
|
||||
val readArb = Module(new Arbiter(new L1DataReadReq, 4))
|
||||
val writeArb = Module(new Arbiter(new L1DataWriteReq, 2))
|
||||
data.io.write.valid := writeArb.io.out.valid
|
||||
writeArb.io.out.ready := data.io.write.ready
|
||||
data.io.write.bits := writeArb.io.out.bits
|
||||
@ -837,9 +769,9 @@ class HellaCache extends L1HellaCacheModule {
|
||||
}
|
||||
|
||||
writeArb.io.in(0).bits.addr := s3_req.addr
|
||||
writeArb.io.in(0).bits.wmask := UInt(1) << (if(rowOffBits > offsetlsb)
|
||||
s3_req.addr(rowOffBits-1,offsetlsb).toUInt
|
||||
else UInt(0))
|
||||
val rowIdx = s3_req.addr(rowOffBits-1,offsetlsb).toUInt
|
||||
val rowWMask = UInt(1) << (if(rowOffBits > offsetlsb) rowIdx else UInt(0))
|
||||
writeArb.io.in(0).bits.wmask := rowWMask
|
||||
writeArb.io.in(0).bits.data := Fill(rowWords, s3_req.data)
|
||||
writeArb.io.in(0).valid := s3_valid
|
||||
writeArb.io.in(0).bits.way_en := s3_way
|
||||
@ -871,7 +803,7 @@ class HellaCache extends L1HellaCacheModule {
|
||||
metaWriteArb.io.in(0) <> mshrs.io.meta_write
|
||||
|
||||
// probes and releases
|
||||
val releaseArb = Module(new LockingArbiter(new Release, 2, outerDataBeats, co.messageHasData _))
|
||||
val releaseArb = Module(new LockingArbiter(new Release, 2, outerDataBeats, (r: Release) => r.hasMultibeatData()))
|
||||
DecoupledLogicalNetworkIOWrapper(releaseArb.io.out) <> io.mem.release
|
||||
|
||||
val probe = DecoupledLogicalNetworkIOUnwrapper(io.mem.probe)
|
||||
@ -886,14 +818,15 @@ class HellaCache extends L1HellaCacheModule {
|
||||
prober.io.mshr_rdy := mshrs.io.probe_rdy
|
||||
|
||||
// refills
|
||||
def doRefill(g: Grant): Bool = co.messageUpdatesDataArray(g)
|
||||
val ser = Module(new FlowThroughSerializer(io.mem.grant.bits, refillCyclesPerBeat, doRefill))
|
||||
val ser = Module(new FlowThroughSerializer(
|
||||
io.mem.grant.bits,
|
||||
refillCyclesPerBeat))
|
||||
ser.io.in <> io.mem.grant
|
||||
val refill = ser.io.out
|
||||
mshrs.io.mem_grant.valid := refill.fire()
|
||||
mshrs.io.mem_grant.bits := refill.bits
|
||||
refill.ready := writeArb.io.in(1).ready || !doRefill(refill.bits.payload)
|
||||
writeArb.io.in(1).valid := refill.valid && doRefill(refill.bits.payload)
|
||||
refill.ready := writeArb.io.in(1).ready || !refill.bits.payload.hasData()
|
||||
writeArb.io.in(1).valid := refill.valid && refill.bits.payload.hasData()
|
||||
writeArb.io.in(1).bits := mshrs.io.mem_resp
|
||||
writeArb.io.in(1).bits.wmask := SInt(-1)
|
||||
writeArb.io.in(1).bits.data := refill.bits.payload.data(encRowBits-1,0)
|
||||
@ -1008,15 +941,15 @@ class SimpleHellaCacheIF extends Module
|
||||
io.cache.req.bits.data := RegEnable(req_arb.io.out.bits.data, s0_req_fire)
|
||||
io.cache.req <> req_arb.io.out
|
||||
|
||||
// replay queues
|
||||
// replayq1 holds the older request
|
||||
// replayq2 holds the newer request (for the first nack)
|
||||
// we need to split the queues like this for the case where the older request
|
||||
// goes through but gets nacked, while the newer request stalls
|
||||
// if this happens, the newer request will go through before the older
|
||||
// request
|
||||
// we don't need to check replayq1.io.enq.ready and replayq2.io.enq.ready as
|
||||
// there will only be two requests going through at most
|
||||
/* replay queues:
|
||||
replayq1 holds the older request.
|
||||
replayq2 holds the newer request (for the first nack).
|
||||
We need to split the queues like this for the case where the older request
|
||||
goes through but gets nacked, while the newer request stalls.
|
||||
If this happens, the newer request will go through before the older one.
|
||||
We don't need to check replayq1.io.enq.ready and replayq2.io.enq.ready as
|
||||
there will only be two requests going through at most.
|
||||
*/
|
||||
|
||||
// stash d$ request in stage 2 if nacked (older request)
|
||||
replayq1.io.enq.valid := Bool(false)
|
||||
|
||||
Reference in New Issue
Block a user