riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

dir supplied by function

Browse Source
This commit is contained in:
Henry Cook
2014-09-24 12:04:11 -07:00
committed by Yunsup Lee
parent db4de7b806
commit 7398b00d93
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/PublicConfigs.scala
View File

@@ -126,7 +126,7 @@ class DefaultConfig extends ChiselConfig {
}
}
case Coherence => {
val dir = new FullRepresentation(site(NClients))
val dir = () => new FullRepresentation(site(NClients))
val enSharing = site[Boolean]("ENABLE_SHARING")
val enCleanEx = site[Boolean]("ENABLE_CLEAN_EXCLUSIVE")
if(enSharing) {