riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

aggressively clock gate int and fp datapaths

Browse Source
This commit is contained in:
Andrew Waterman 2012-11-04 16:40:14 -08:00
parent bd2d61de03
commit 7380c9fe60
8 changed files with 568 additions and 639 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
rocket/src/main/scala/consts.scala
View File

@ -16,14 +16,14 @@ abstract trait TileConfigConstants {
trait ScalarOpConstants { trait ScalarOpConstants {
val BR_X = Bits("b???", 3) val BR_X = Bits("b???", 3)
val BR_EQ = UFix(0, 3) val BR_EQ = Bits(0, 3)
val BR_NE = UFix(1, 3) val BR_NE = Bits(1, 3)
val BR_J = UFix(2, 3) val BR_J = Bits(2, 3)
val BR_N = UFix(3, 3) val BR_N = Bits(3, 3)
val BR_LT = UFix(4, 3) val BR_LT = Bits(4, 3)
val BR_GE = UFix(5, 3) val BR_GE = Bits(5, 3)
val BR_LTU = UFix(6, 3) val BR_LTU = Bits(6, 3)
val BR_GEU = UFix(7, 3) val BR_GEU = Bits(7, 3)
val PC_EX4 = UFix(0, 2) val PC_EX4 = UFix(0, 2)
val PC_EX = UFix(1, 2) val PC_EX = UFix(1, 2)

374
rocket/src/main/scala/ctrl.scala
View File

@ -11,25 +11,21 @@ class ioCtrlDpath extends Bundle()
{ {
// outputs to datapath // outputs to datapath
val sel_pc = UFix(OUTPUT, 3); val sel_pc = UFix(OUTPUT, 3);
val stalld = Bool(OUTPUT);
val killd = Bool(OUTPUT); val killd = Bool(OUTPUT);
val killx = Bool(OUTPUT);
val killm = Bool(OUTPUT);
val ren2 = Bool(OUTPUT); val ren2 = Bool(OUTPUT);
val ren1 = Bool(OUTPUT); val ren1 = Bool(OUTPUT);
val sel_alu2 = UFix(OUTPUT, 3); val sel_alu2 = UFix(OUTPUT, 3);
val fn_dw = Bool(OUTPUT); val fn_dw = Bool(OUTPUT);
val fn_alu = UFix(OUTPUT, 4); val fn_alu = UFix(OUTPUT, 4);
val mul_val = Bool(OUTPUT); val mul_val = Bool(OUTPUT);
val mul_fn = UFix(OUTPUT, 2); val mul_fn = Bits(OUTPUT, 2);
val mul_kill = Bool(OUTPUT) val mul_kill = Bool(OUTPUT)
val div_val = Bool(OUTPUT); val div_val = Bool(OUTPUT);
val div_fn = UFix(OUTPUT, 2); val div_fn = Bits(OUTPUT, 2);
val div_kill = Bool(OUTPUT) val div_kill = Bool(OUTPUT)
val sel_wa = Bool(OUTPUT); val sel_wa = Bool(OUTPUT);
val sel_wb = UFix(OUTPUT, 3); val sel_wb = UFix(OUTPUT, 3);
val pcr = UFix(OUTPUT, 3) val pcr = UFix(OUTPUT, 3)
val id_eret = Bool(OUTPUT);
val wb_eret = Bool(OUTPUT); val wb_eret = Bool(OUTPUT);
val mem_load = Bool(OUTPUT); val mem_load = Bool(OUTPUT);
val ex_fp_val= Bool(OUTPUT); val ex_fp_val= Bool(OUTPUT);
@ -40,7 +36,7 @@ class ioCtrlDpath extends Bundle()
val wb_wen = Bool(OUTPUT); val wb_wen = Bool(OUTPUT);
val wb_valid = Bool(OUTPUT) val wb_valid = Bool(OUTPUT)
val flush_inst = Bool(OUTPUT); val flush_inst = Bool(OUTPUT);
val ex_mem_type = UFix(OUTPUT, 3) val ex_mem_type = Bits(OUTPUT, 3)
// exception handling // exception handling
val exception = Bool(OUTPUT); val exception = Bool(OUTPUT);
val cause = UFix(OUTPUT, 6); val cause = UFix(OUTPUT, 6);
@ -184,20 +180,20 @@ object rocketCtrlXDecode extends rocketCtrlDecodeConstants
SRLW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32,FN_SR, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), SRLW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32,FN_SR, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
SRAW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32,FN_SRA, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), SRAW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32,FN_SRA, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
MUL-> List(Y, N,N,BR_N, N,Y,Y,A2_X, DW_XPR,FN_X, N,M_X, MT_X, Y,MUL_LO, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), MUL-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, Y,MUL_LO, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
MULH-> List(Y, N,N,BR_N, N,Y,Y,A2_X, DW_XPR,FN_X, N,M_X, MT_X, Y,MUL_H, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), MULH-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, Y,MUL_H, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
MULHU-> List(Y, N,N,BR_N, N,Y,Y,A2_X, DW_XPR,FN_X, N,M_X, MT_X, Y,MUL_HU, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), MULHU-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, Y,MUL_HU, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
MULHSU-> List(Y, N,N,BR_N, N,Y,Y,A2_X, DW_XPR,FN_X, N,M_X, MT_X, Y,MUL_HSU,N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), MULHSU-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, Y,MUL_HSU,N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
MULW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_X, DW_32, FN_X, N,M_X, MT_X, Y,MUL_LO, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), MULW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32, FN_X, N,M_X, MT_X, Y,MUL_LO, N,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
DIV-> List(Y, N,N,BR_N, N,Y,Y,A2_X, DW_XPR,FN_X, N,M_X, MT_X, N,DIV_D, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), DIV-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, N,DIV_D, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
DIVU-> List(Y, N,N,BR_N, N,Y,Y,A2_X, DW_XPR,FN_X, N,M_X, MT_X, N,DIV_DU, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), DIVU-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, N,DIV_DU, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
REM-> List(Y, N,N,BR_N, N,Y,Y,A2_X, DW_XPR,FN_X, N,M_X, MT_X, N,DIV_R, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), REM-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, N,DIV_R, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
REMU-> List(Y, N,N,BR_N, N,Y,Y,A2_X, DW_XPR,FN_X, N,M_X, MT_X, N,DIV_RU, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), REMU-> List(Y, N,N,BR_N, N,Y,Y,A2_RTYPE,DW_XPR,FN_X, N,M_X, MT_X, N,DIV_RU, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
DIVW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_X, DW_32, FN_X, N,M_X, MT_X, N,DIV_D, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), DIVW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32, FN_X, N,M_X, MT_X, N,DIV_D, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
DIVUW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_X, DW_32, FN_X, N,M_X, MT_X, N,DIV_DU, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), DIVUW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32, FN_X, N,M_X, MT_X, N,DIV_DU, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
REMW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_X, DW_32, FN_X, N,M_X, MT_X, N,DIV_R, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), REMW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32, FN_X, N,M_X, MT_X, N,DIV_R, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
REMUW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_X, DW_32, FN_X, N,M_X, MT_X, N,DIV_RU, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N), REMUW-> List(xpr64,N,N,BR_N, N,Y,Y,A2_RTYPE,DW_32, FN_X, N,M_X, MT_X, N,DIV_RU, Y,Y,WA_RD,WB_X, PCR_N,SYNC_N,N,N,N,N),
SYSCALL-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_N,N,Y,N,N), SYSCALL-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_X, FN_X, N,M_X, MT_X, N,MUL_X, N,N,WA_X, WB_X, PCR_N,SYNC_N,N,Y,N,N),
SETPCR-> List(Y, N,N,BR_N, N,N,N,A2_ITYPE,DW_XPR,FN_OP2, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_S,SYNC_N,N,N,Y,Y), SETPCR-> List(Y, N,N,BR_N, N,N,N,A2_ITYPE,DW_XPR,FN_OP2, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_ALU,PCR_S,SYNC_N,N,N,Y,Y),
@ -358,77 +354,74 @@ class rocketCtrl extends Component
val id_waddr = Mux(id_sel_wa === WA_RA, RA, io.dpath.inst(31,27)); val id_waddr = Mux(id_sel_wa === WA_RA, RA, io.dpath.inst(31,27));
val id_load_use = Bool(); val id_load_use = Bool();
val ex_reg_br_type = Reg(){Bits()} val ex_reg_xcpt_interrupt = Reg(resetVal = Bool(false))
val ex_reg_jalr = Reg(){Bool()} val ex_reg_valid = Reg(resetVal = Bool(false))
val ex_reg_btb_hit = Reg(){Bool()}; val ex_reg_eret = Reg(resetVal = Bool(false))
val ex_reg_div_val = Reg(){Bool()}; val ex_reg_wen = Reg(resetVal = Bool(false))
val ex_reg_mul_val = Reg(){Bool()}; val ex_reg_fp_wen = Reg(resetVal = Bool(false))
val ex_reg_mul_fn = Reg(){UFix()}; val ex_reg_flush_inst = Reg(resetVal = Bool(false))
val ex_reg_mem_val = Reg(){Bool()}; val ex_reg_jalr = Reg(resetVal = Bool(false))
val ex_reg_mem_cmd = Reg(){Bits()}; val ex_reg_btb_hit = Reg(resetVal = Bool(false))
val ex_reg_mem_type = Reg(){UFix(width = 3)}; val ex_reg_div_val = Reg(resetVal = Bool(false))
val ex_reg_valid = Reg(resetVal = Bool(false)); val ex_reg_mul_val = Reg(resetVal = Bool(false))
val ex_reg_pcr = Reg(resetVal = PCR_N); val ex_reg_mem_val = Reg(resetVal = Bool(false))
val ex_reg_wen = Reg(resetVal = Bool(false)); val ex_reg_xcpt = Reg(resetVal = Bool(false))
val ex_reg_fp_wen = Reg(resetVal = Bool(false)); val ex_reg_fp_val = Reg(resetVal = Bool(false))
val ex_reg_eret = Reg(resetVal = Bool(false)); val ex_reg_vec_val = Reg(resetVal = Bool(false))
val ex_reg_flush_inst = Reg(resetVal = Bool(false)); val ex_reg_replay_next = Reg(resetVal = Bool(false))
val ex_reg_xcpt_interrupt = Reg(resetVal = Bool(false)); val ex_reg_load_use = Reg(resetVal = Bool(false))
val ex_reg_pcr = Reg(resetVal = PCR_N)
val ex_reg_br_type = Reg(resetVal = BR_N)
val ex_reg_mul_fn = Reg(){Bits()}
val ex_reg_mem_cmd = Reg(){Bits()}
val ex_reg_mem_type = Reg(){Bits()}
val ex_reg_cause = Reg(){UFix()} val ex_reg_cause = Reg(){UFix()}
val ex_reg_xcpt_ma_inst = Reg(resetVal = Bool(false));
val ex_reg_xcpt_itlb = Reg(resetVal = Bool(false));
val ex_reg_xcpt_illegal = Reg(resetVal = Bool(false));
val ex_reg_xcpt_privileged = Reg(resetVal = Bool(false));
val ex_reg_xcpt_syscall = Reg(resetVal = Bool(false));
val ex_reg_fp_val = Reg(resetVal = Bool(false));
val ex_reg_fp_sboard_set = Reg(resetVal = Bool(false));
val ex_reg_vec_val = Reg(resetVal = Bool(false));
val ex_reg_replay_next = Reg(resetVal = Bool(false));
val ex_reg_load_use = Reg(resetVal = Bool(false));
val mem_reg_valid = Reg(resetVal = Bool(false)); val mem_reg_xcpt_interrupt = Reg(resetVal = Bool(false))
val mem_reg_pcr = Reg(resetVal = PCR_N); val mem_reg_valid = Reg(resetVal = Bool(false))
val mem_reg_wen = Reg(resetVal = Bool(false)); val mem_reg_eret = Reg(resetVal = Bool(false))
val mem_reg_fp_wen = Reg(resetVal = Bool(false)); val mem_reg_wen = Reg(resetVal = Bool(false))
val mem_reg_flush_inst = Reg(resetVal = Bool(false)); val mem_reg_fp_wen = Reg(resetVal = Bool(false))
val mem_reg_xcpt_interrupt = Reg(resetVal = Bool(false)); val mem_reg_flush_inst = Reg(resetVal = Bool(false))
val mem_reg_div_val = Reg(resetVal = Bool(false))
val mem_reg_mul_val = Reg(resetVal = Bool(false))
val mem_reg_mem_val = Reg(resetVal = Bool(false))
val mem_reg_xcpt = Reg(resetVal = Bool(false))
val mem_reg_fp_val = Reg(resetVal = Bool(false))
val mem_reg_replay = Reg(resetVal = Bool(false))
val mem_reg_replay_next = Reg(resetVal = Bool(false))
val mem_reg_pcr = Reg(resetVal = PCR_N)
val mem_reg_cause = Reg(){UFix()} val mem_reg_cause = Reg(){UFix()}
val mem_reg_xcpt_ma_inst = Reg(resetVal = Bool(false)); val mem_reg_mem_type = Reg(){Bits()}
val mem_reg_xcpt_itlb = Reg(resetVal = Bool(false));
val mem_reg_xcpt_illegal = Reg(resetVal = Bool(false));
val mem_reg_xcpt_privileged = Reg(resetVal = Bool(false));
val mem_reg_xcpt_fpu = Reg(resetVal = Bool(false));
val mem_reg_xcpt_vec = Reg(resetVal = Bool(false));
val mem_reg_xcpt_syscall = Reg(resetVal = Bool(false));
val mem_reg_fp_val = Reg(resetVal = Bool(false));
val mem_reg_replay = Reg(resetVal = Bool(false));
val mem_reg_replay_next = Reg(resetVal = Bool(false));
val mem_reg_kill = Reg(resetVal = Bool(false));
val mem_reg_fp_sboard_set = Reg(resetVal = Bool(false));
val wb_reg_valid = Reg(resetVal = Bool(false));
val wb_reg_pcr = Reg(resetVal = PCR_N); val wb_reg_valid = Reg(resetVal = Bool(false))
val wb_reg_wen = Reg(resetVal = Bool(false)); val wb_reg_pcr = Reg(resetVal = PCR_N)
val wb_reg_fp_wen = Reg(resetVal = Bool(false)); val wb_reg_wen = Reg(resetVal = Bool(false))
val wb_reg_flush_inst = Reg(resetVal = Bool(false)); val wb_reg_fp_wen = Reg(resetVal = Bool(false))
val wb_reg_eret = Reg(resetVal = Bool(false)); val wb_reg_flush_inst = Reg(resetVal = Bool(false))
val wb_reg_exception = Reg(resetVal = Bool(false)); val wb_reg_eret = Reg(resetVal = Bool(false))
val wb_reg_replay = Reg(resetVal = Bool(false)); val wb_reg_xcpt = Reg(resetVal = Bool(false))
val wb_reg_replay_next = Reg(resetVal = Bool(false)); val wb_reg_replay = Reg(resetVal = Bool(false))
val wb_reg_cause = Reg(){UFix()}; val wb_reg_replay_next = Reg(resetVal = Bool(false))
val wb_reg_fp_val = Reg(resetVal = Bool(false)); val wb_reg_cause = Reg(){UFix()}
val wb_reg_fp_sboard_set = Reg(resetVal = Bool(false)); val wb_reg_fp_val = Reg(resetVal = Bool(false))
val wb_reg_dcache_miss = Reg(io.dmem.resp.bits.miss || io.dmem.resp.bits.nack, resetVal = Bool(false)); val wb_reg_dcache_miss = Reg(io.dmem.resp.bits.miss || io.dmem.resp.bits.nack, resetVal = Bool(false))
val wb_reg_div_mul_val = Reg(resetVal = Bool(false)) val wb_reg_div_mul_val = Reg(resetVal = Bool(false))
val take_pc = Bool() val take_pc = Bool()
val take_pc_wb = Bool() val take_pc_wb = Bool()
val ctrl_killd = Bool()
val ctrl_killx = Bool()
val ctrl_killm = Bool() val ctrl_killm = Bool()
val id_maskable_interrupts = List(
(io.dpath.irq_ipi, IRQ_IPI),
(io.dpath.irq_timer, IRQ_TIMER))
var id_interrupts = id_maskable_interrupts.map(i => (io.dpath.status(SR_IM+i._2) && i._1, UFix(CAUSE_INTERRUPT+i._2)))
var vec_replay = Bool(false) var vec_replay = Bool(false)
var vec_stalld = Bool(false) var vec_stalld = Bool(false)
var vec_irq = Bool(false)
var vec_irq_cause = UFix(CAUSE_INTERRUPT+IRQ_IPI) // don't care
if (HAVE_VEC) if (HAVE_VEC)
{ {
// vector control // vector control
@ -440,7 +433,7 @@ class rocketCtrl extends Component
vec.io.valid := wb_reg_valid vec.io.valid := wb_reg_valid
vec.io.s := io.dpath.status(SR_S) vec.io.s := io.dpath.status(SR_S)
vec.io.sr_ev := io.dpath.status(SR_EV) vec.io.sr_ev := io.dpath.status(SR_EV)
vec.io.exception := wb_reg_exception vec.io.exception := wb_reg_xcpt
vec.io.eret := wb_reg_eret vec.io.eret := wb_reg_eret
val vec_dec = new rocketCtrlVecDecoder() val vec_dec = new rocketCtrlVecDecoder()
@ -463,48 +456,49 @@ class rocketCtrl extends Component
vec_dec.io.sigs.vfence && !vec.io.vfence_ready) vec_dec.io.sigs.vfence && !vec.io.vfence_ready)
vec_replay = vec.io.replay vec_replay = vec.io.replay
vec_irq = vec.io.irq id_interrupts = id_interrupts :+ (vec.io.irq, vec.io.irq_cause)
vec_irq_cause = vec.io.irq_cause
} }
val (id_interrupt_unmasked, id_interrupt_cause) = checkExceptions(id_interrupts)
val id_interrupt = io.dpath.status(SR_ET) && id_interrupt_unmasked
def checkExceptions(x: Seq[(Bits, UFix)]) =
(x.map(_._1).reduce(_||_), PriorityMux(x))
// executing ERET when traps are enabled causes an illegal instruction exception // executing ERET when traps are enabled causes an illegal instruction exception
val illegal_inst = !id_int_val.toBool || (id_eret.toBool && io.dpath.status(SR_ET)) val illegal_inst = !id_int_val.toBool || (id_eret.toBool && io.dpath.status(SR_ET))
val p_irq_timer = (io.dpath.status(SR_IM+IRQ_TIMER).toBool && io.dpath.irq_timer); val (id_xcpt, id_cause) = checkExceptions(List(
val p_irq_ipi = (io.dpath.status(SR_IM+IRQ_IPI).toBool && io.dpath.irq_ipi); (id_interrupt, id_interrupt_cause),
val id_interrupt = (io.imem.resp.bits.xcpt_ma, UFix(0)),
io.dpath.status(SR_ET).toBool && (io.imem.resp.bits.xcpt_if, UFix(1)),
((io.dpath.status(SR_IM+IRQ_TIMER).toBool && io.dpath.irq_timer) || (illegal_inst, UFix(2)),
(io.dpath.status(SR_IM+IRQ_IPI).toBool && io.dpath.irq_ipi) || (id_privileged && !io.dpath.status(SR_S), UFix(3)),
vec_irq); (id_fp_val && !io.dpath.status(SR_EF), UFix(4)),
val id_cause = (id_syscall, UFix(6)),
Mux(p_irq_ipi, UFix(CAUSE_INTERRUPT+IRQ_IPI,6), (id_vec_val && !io.dpath.status(SR_EV), UFix(12))))
Mux(p_irq_timer, UFix(CAUSE_INTERRUPT+IRQ_TIMER,6),
vec_irq_cause))
when (reset.toBool || io.dpath.killd) { ex_reg_xcpt_interrupt := id_interrupt && !take_pc && io.imem.resp.valid
ex_reg_br_type := BR_N; when (id_xcpt) { ex_reg_cause := id_cause }
when (ctrl_killd) {
ex_reg_jalr := Bool(false) ex_reg_jalr := Bool(false)
ex_reg_btb_hit := Bool(false); ex_reg_btb_hit := Bool(false);
ex_reg_div_val := Bool(false); ex_reg_div_val := Bool(false);
ex_reg_mul_val := Bool(false); ex_reg_mul_val := Bool(false);
ex_reg_mem_val := Bool(false); ex_reg_mem_val := Bool(false);
ex_reg_valid := Bool(false); ex_reg_valid := Bool(false);
ex_reg_pcr := PCR_N
ex_reg_wen := Bool(false); ex_reg_wen := Bool(false);
ex_reg_fp_wen := Bool(false); ex_reg_fp_wen := Bool(false);
ex_reg_eret := Bool(false); ex_reg_eret := Bool(false);
ex_reg_flush_inst := Bool(false); ex_reg_flush_inst := Bool(false);
ex_reg_xcpt_ma_inst := Bool(false);
ex_reg_xcpt_itlb := Bool(false);
ex_reg_xcpt_illegal := Bool(false);
ex_reg_xcpt_privileged := Bool(false);
ex_reg_xcpt_syscall := Bool(false);
ex_reg_fp_val := Bool(false); ex_reg_fp_val := Bool(false);
ex_reg_fp_sboard_set := Bool(false);
ex_reg_vec_val := Bool(false); ex_reg_vec_val := Bool(false);
ex_reg_replay_next := Bool(false); ex_reg_replay_next := Bool(false);
ex_reg_load_use := Bool(false); ex_reg_load_use := Bool(false);
ex_reg_pcr := PCR_N
ex_reg_br_type := BR_N
ex_reg_xcpt := Bool(false)
} }
.otherwise { .otherwise {
ex_reg_br_type := id_br_type; ex_reg_br_type := id_br_type;
@ -520,21 +514,14 @@ class rocketCtrl extends Component
ex_reg_fp_wen := id_fp_val && io.fpu.dec.wen ex_reg_fp_wen := id_fp_val && io.fpu.dec.wen
ex_reg_eret := id_eret.toBool; ex_reg_eret := id_eret.toBool;
ex_reg_flush_inst := (id_sync === SYNC_I); ex_reg_flush_inst := (id_sync === SYNC_I);
ex_reg_xcpt_ma_inst := io.imem.resp.bits.xcpt_ma
ex_reg_xcpt_itlb := io.imem.resp.bits.xcpt_if
ex_reg_xcpt_illegal := illegal_inst;
ex_reg_xcpt_privileged := (id_privileged & ~io.dpath.status(SR_S)).toBool;
ex_reg_xcpt_syscall := id_syscall.toBool;
ex_reg_fp_val := id_fp_val ex_reg_fp_val := id_fp_val
ex_reg_fp_sboard_set := io.fpu.dec.sboard
ex_reg_vec_val := id_vec_val.toBool ex_reg_vec_val := id_vec_val.toBool
ex_reg_replay_next := id_replay_next ex_reg_replay_next := id_replay_next
ex_reg_load_use := id_load_use; ex_reg_load_use := id_load_use;
ex_reg_mem_cmd := id_mem_cmd
ex_reg_mem_type := id_mem_type.toUFix
ex_reg_xcpt := id_xcpt
} }
ex_reg_xcpt_interrupt := !take_pc && id_interrupt
ex_reg_mem_cmd := id_mem_cmd
ex_reg_mem_type := id_mem_type.toUFix
ex_reg_cause := id_cause
val br_taken = val br_taken =
Mux(ex_reg_br_type === BR_EQ, io.dpath.br_eq, Mux(ex_reg_br_type === BR_EQ, io.dpath.br_eq,
@ -544,15 +531,18 @@ class rocketCtrl extends Component
Mux(ex_reg_br_type === BR_LTU, io.dpath.br_ltu, Mux(ex_reg_br_type === BR_LTU, io.dpath.br_ltu,
Mux(ex_reg_br_type === BR_GEU, ~io.dpath.br_ltu, Mux(ex_reg_br_type === BR_GEU, ~io.dpath.br_ltu,
ex_reg_br_type === BR_J)))))) ex_reg_br_type === BR_J))))))
val take_pc_ex = !Mux(ex_reg_jalr, ex_reg_btb_hit && io.dpath.jalr_eq, ex_reg_btb_hit === br_taken)
val mem_reg_div_val = Reg(resetVal = Bool(false))
val mem_reg_mul_val = Reg(resetVal = Bool(false))
val mem_reg_eret = Reg(){Bool()};
val mem_reg_mem_val = Reg(){Bool()};
val mem_reg_mem_cmd = Reg(){Bits()}
val mem_reg_mem_type = Reg(){Bits()}
when (reset.toBool || io.dpath.killx) { val (ex_xcpt, ex_cause) = checkExceptions(List(
(ex_reg_xcpt_interrupt || ex_reg_xcpt, ex_reg_cause),
(ex_reg_fp_val && io.fpu.illegal_rm, UFix(2))))
mem_reg_xcpt_interrupt := ex_reg_xcpt_interrupt && !take_pc_wb
when (ex_xcpt) { mem_reg_cause := ex_cause }
mem_reg_div_val := ex_reg_div_val && io.dpath.div_rdy
mem_reg_mul_val := ex_reg_mul_val && io.dpath.mul_rdy
when (ctrl_killx) {
mem_reg_valid := Bool(false); mem_reg_valid := Bool(false);
mem_reg_pcr := PCR_N mem_reg_pcr := PCR_N
mem_reg_wen := Bool(false); mem_reg_wen := Bool(false);
@ -560,16 +550,9 @@ class rocketCtrl extends Component
mem_reg_eret := Bool(false); mem_reg_eret := Bool(false);
mem_reg_mem_val := Bool(false); mem_reg_mem_val := Bool(false);
mem_reg_flush_inst := Bool(false); mem_reg_flush_inst := Bool(false);
mem_reg_xcpt_ma_inst := Bool(false);
mem_reg_xcpt_itlb := Bool(false);
mem_reg_xcpt_illegal := Bool(false);
mem_reg_xcpt_privileged := Bool(false);
mem_reg_xcpt_fpu := Bool(false);
mem_reg_xcpt_vec := Bool(false);
mem_reg_xcpt_syscall := Bool(false);
mem_reg_fp_val := Bool(false); mem_reg_fp_val := Bool(false);
mem_reg_fp_sboard_set := Bool(false)
mem_reg_replay_next := Bool(false) mem_reg_replay_next := Bool(false)
mem_reg_xcpt := Bool(false)
} }
.otherwise { .otherwise {
mem_reg_valid := ex_reg_valid mem_reg_valid := ex_reg_valid
@ -579,23 +562,21 @@ class rocketCtrl extends Component
mem_reg_eret := ex_reg_eret; mem_reg_eret := ex_reg_eret;
mem_reg_mem_val := ex_reg_mem_val; mem_reg_mem_val := ex_reg_mem_val;
mem_reg_flush_inst := ex_reg_flush_inst; mem_reg_flush_inst := ex_reg_flush_inst;
mem_reg_xcpt_ma_inst := ex_reg_xcpt_ma_inst;
mem_reg_xcpt_itlb := ex_reg_xcpt_itlb;
mem_reg_xcpt_illegal := ex_reg_xcpt_illegal || ex_reg_fp_val && io.fpu.illegal_rm;
mem_reg_xcpt_privileged := ex_reg_xcpt_privileged;
mem_reg_xcpt_fpu := ex_reg_fp_val && !io.dpath.status(SR_EF).toBool;
mem_reg_xcpt_vec := ex_reg_vec_val && !io.dpath.status(SR_EV).toBool;
mem_reg_xcpt_syscall := ex_reg_xcpt_syscall;
mem_reg_fp_val := ex_reg_fp_val mem_reg_fp_val := ex_reg_fp_val
mem_reg_fp_sboard_set := ex_reg_fp_sboard_set
mem_reg_replay_next := ex_reg_replay_next mem_reg_replay_next := ex_reg_replay_next
mem_reg_mem_type := ex_reg_mem_type
mem_reg_xcpt := ex_xcpt
} }
mem_reg_div_val := ex_reg_div_val && io.dpath.div_rdy
mem_reg_mul_val := ex_reg_mul_val && io.dpath.mul_rdy val (mem_xcpt, mem_cause) = checkExceptions(List(
mem_reg_mem_cmd := ex_reg_mem_cmd; (mem_reg_xcpt_interrupt || mem_reg_xcpt, mem_reg_cause),
mem_reg_mem_type := ex_reg_mem_type; (mem_reg_mem_val && io.dmem.xcpt.ma.ld, UFix( 8)),
mem_reg_xcpt_interrupt := ex_reg_xcpt_interrupt && !take_pc_wb (mem_reg_mem_val && io.dmem.xcpt.ma.st, UFix( 9)),
mem_reg_cause := ex_reg_cause (mem_reg_mem_val && io.xcpt_dtlb_ld, UFix(10)),
(mem_reg_mem_val && io.xcpt_dtlb_st, UFix(11))))
wb_reg_xcpt := mem_xcpt && !take_pc_wb && !wb_reg_replay_next
when (mem_xcpt) { wb_reg_cause := mem_cause }
when (ctrl_killm) { when (ctrl_killm) {
wb_reg_valid := Bool(false) wb_reg_valid := Bool(false)
@ -606,7 +587,6 @@ class rocketCtrl extends Component
wb_reg_flush_inst := Bool(false); wb_reg_flush_inst := Bool(false);
wb_reg_div_mul_val := Bool(false); wb_reg_div_mul_val := Bool(false);
wb_reg_fp_val := Bool(false) wb_reg_fp_val := Bool(false)
wb_reg_fp_sboard_set := Bool(false)
wb_reg_replay_next := Bool(false) wb_reg_replay_next := Bool(false)
} }
.otherwise { .otherwise {
@ -618,7 +598,6 @@ class rocketCtrl extends Component
wb_reg_flush_inst := mem_reg_flush_inst; wb_reg_flush_inst := mem_reg_flush_inst;
wb_reg_div_mul_val := mem_reg_div_val || mem_reg_mul_val wb_reg_div_mul_val := mem_reg_div_val || mem_reg_mul_val
wb_reg_fp_val := mem_reg_fp_val wb_reg_fp_val := mem_reg_fp_val
wb_reg_fp_sboard_set := mem_reg_fp_sboard_set
wb_reg_replay_next := mem_reg_replay_next wb_reg_replay_next := mem_reg_replay_next
} }
@ -648,7 +627,7 @@ class rocketCtrl extends Component
fp_sboard.io.r(2).addr := id_raddr3.toUFix fp_sboard.io.r(2).addr := id_raddr3.toUFix
fp_sboard.io.r(3).addr := id_waddr.toUFix fp_sboard.io.r(3).addr := id_waddr.toUFix
fp_sboard.io.w(0).en := wb_reg_dcache_miss && wb_reg_fp_wen || wb_reg_fp_sboard_set fp_sboard.io.w(0).en := wb_reg_dcache_miss && wb_reg_fp_wen || io.fpu.sboard_set
fp_sboard.io.w(0).data := Bool(true) fp_sboard.io.w(0).data := Bool(true)
fp_sboard.io.w(0).addr := io.dpath.fp_sboard_wb_waddr fp_sboard.io.w(0).addr := io.dpath.fp_sboard_wb_waddr
@ -666,82 +645,41 @@ class rocketCtrl extends Component
io.fpu.dec.wen && fp_sboard.io.r(3).data io.fpu.dec.wen && fp_sboard.io.r(3).data
} }
// exception handling // replay inst in ex stage
val mem_xcpt_ma_ld = io.dmem.xcpt.ma.ld && !mem_reg_kill
val mem_xcpt_ma_st = io.dmem.xcpt.ma.st && !mem_reg_kill
val mem_xcpt_dtlb_ld = io.xcpt_dtlb_ld && !mem_reg_kill
val mem_xcpt_dtlb_st = io.xcpt_dtlb_st && !mem_reg_kill
val mem_exception =
mem_reg_xcpt_interrupt ||
mem_xcpt_ma_ld ||
mem_xcpt_ma_st ||
mem_xcpt_dtlb_ld ||
mem_xcpt_dtlb_st ||
mem_reg_xcpt_illegal ||
mem_reg_xcpt_privileged ||
mem_reg_xcpt_fpu ||
mem_reg_xcpt_vec ||
mem_reg_xcpt_syscall ||
mem_reg_xcpt_itlb ||
mem_reg_xcpt_ma_inst;
val mem_cause =
Mux(mem_reg_xcpt_interrupt, mem_reg_cause, // asynchronous interrupt
Mux(mem_reg_xcpt_itlb, UFix(1,5), // instruction access fault
Mux(mem_reg_xcpt_illegal, UFix(2,5), // illegal instruction
Mux(mem_reg_xcpt_privileged, UFix(3,5), // privileged instruction
Mux(mem_reg_xcpt_fpu, UFix(4,5), // FPU disabled
Mux(mem_reg_xcpt_syscall, UFix(6,5), // system call
// breakpoint
Mux(mem_xcpt_ma_ld, UFix(8,5), // misaligned load
Mux(mem_xcpt_ma_st, UFix(9,5), // misaligned store
Mux(mem_xcpt_dtlb_ld, UFix(10,5), // load fault
Mux(mem_xcpt_dtlb_st, UFix(11,5), // store fault
Mux(mem_reg_xcpt_vec, UFix(12,5), // vector disabled
UFix(0,5)))))))))))); // instruction address misaligned
// control transfer from ex/mem
val take_pc_ex = !Mux(ex_reg_jalr, ex_reg_btb_hit && io.dpath.jalr_eq, ex_reg_btb_hit === br_taken)
take_pc_wb := wb_reg_replay || vec_replay || wb_reg_exception || wb_reg_eret
take_pc := take_pc_ex || take_pc_wb;
// replay mem stage PC on a DTLB miss or a long-latency writeback
val mem_ll_wb = io.dpath.mem_wb || io.dpath.mul_result_val || io.dpath.div_result_val
val dmem_kill_mem = mem_reg_valid && (io.dtlb_miss || io.dmem.resp.bits.nack)
val fpu_kill_mem = mem_reg_fp_val && io.fpu.nack_mem
val replay_mem = dmem_kill_mem || mem_reg_wen && mem_ll_wb || mem_reg_replay || fpu_kill_mem
val killm_common = mem_reg_wen && mem_ll_wb || take_pc_wb || mem_exception || mem_reg_kill
ctrl_killm := killm_common || dmem_kill_mem || fpu_kill_mem
// replay execute stage PC when the D$ is blocked, when the D$ misses,
// for privileged instructions, and for fence.i instructions
val replay_ex = wb_reg_dcache_miss && ex_reg_load_use || mem_reg_flush_inst || val replay_ex = wb_reg_dcache_miss && ex_reg_load_use || mem_reg_flush_inst ||
ex_reg_mem_val && !(io.dmem.req.ready && io.dtlb_rdy) || ex_reg_mem_val && !(io.dmem.req.ready && io.dtlb_rdy) ||
ex_reg_div_val && !io.dpath.div_rdy || ex_reg_div_val && !io.dpath.div_rdy ||
ex_reg_mul_val && !io.dpath.mul_rdy || ex_reg_mul_val && !io.dpath.mul_rdy ||
mem_reg_replay_next mem_reg_replay_next
val kill_ex = take_pc_wb || replay_ex ctrl_killx := take_pc_wb || replay_ex
// replay inst in mem stage
val mem_ll_wb = io.dpath.mem_wb || io.dpath.mul_result_val || io.dpath.div_result_val
val dmem_kill_mem = mem_reg_valid && (io.dtlb_miss || io.dmem.resp.bits.nack)
val fpu_kill_mem = mem_reg_fp_val && io.fpu.nack_mem
val replay_mem = dmem_kill_mem || mem_reg_wen && mem_ll_wb || mem_reg_replay || fpu_kill_mem
val killm_common = mem_reg_wen && mem_ll_wb || take_pc_wb || mem_reg_xcpt || !mem_reg_valid
ctrl_killm := killm_common || mem_xcpt || dmem_kill_mem || fpu_kill_mem
mem_reg_replay := replay_ex && !take_pc_wb; mem_reg_replay := replay_ex && !take_pc_wb;
mem_reg_kill := kill_ex;
wb_reg_replay := replay_mem && !take_pc_wb wb_reg_replay := replay_mem && !take_pc_wb
wb_reg_exception := mem_exception && !take_pc_wb && !wb_reg_replay_next
wb_reg_cause := mem_cause;
val replay_wb = wb_reg_replay || vec_replay || io.dpath.pcr_replay val replay_wb = wb_reg_replay || vec_replay || io.dpath.pcr_replay
val wb_badvaddr_wen = wb_reg_exception && ((wb_reg_cause === UFix(10)) || (wb_reg_cause === UFix(11)))
// write cause to PCR on an exception // write cause to PCR on an exception
io.dpath.exception := wb_reg_exception; io.dpath.exception := wb_reg_xcpt
io.dpath.cause := wb_reg_cause; io.dpath.cause := wb_reg_cause
io.dpath.badvaddr_wen := wb_badvaddr_wen; io.dpath.badvaddr_wen := wb_reg_xcpt && (wb_reg_cause === UFix(10) || wb_reg_cause === UFix(11))
io.dpath.vec_irq_aux_wen := wb_reg_exception && wb_reg_cause >= UFix(24) && wb_reg_cause < UFix(32) io.dpath.vec_irq_aux_wen := wb_reg_xcpt && wb_reg_cause >= UFix(24) && wb_reg_cause < UFix(32)
// control transfer from ex/wb
take_pc_wb := wb_reg_replay || vec_replay || wb_reg_xcpt || wb_reg_eret
take_pc := take_pc_ex || take_pc_wb;
io.dpath.sel_pc := io.dpath.sel_pc :=
Mux(wb_reg_exception, PC_PCR, // exception Mux(wb_reg_xcpt, PC_PCR, // exception
Mux(wb_reg_eret, PC_PCR, // eret instruction Mux(wb_reg_eret, PC_PCR, // eret instruction
Mux(replay_wb, PC_WB, // replay Mux(replay_wb, PC_WB, // replay
Mux(ex_reg_jalr, PC_EX, // JALR Mux(ex_reg_jalr, PC_EX, // JALR
@ -795,9 +733,6 @@ class rocketCtrl extends Component
val id_wb_hazard = data_hazard_wb && (wb_reg_dcache_miss || wb_reg_div_mul_val) || val id_wb_hazard = data_hazard_wb && (wb_reg_dcache_miss || wb_reg_div_mul_val) ||
fp_data_hazard_wb && (wb_reg_dcache_miss || wb_reg_fp_val) fp_data_hazard_wb && (wb_reg_dcache_miss || wb_reg_fp_val)
val killd_common = take_pc || id_interrupt || ex_reg_replay_next
val ctrl_killd = killd_common || !io.imem.resp.valid
val ctrl_stalld = val ctrl_stalld =
id_ex_hazard || id_mem_hazard || id_wb_hazard || id_ex_hazard || id_mem_hazard || id_wb_hazard ||
id_stall_raddr1 || id_stall_raddr2 || id_stall_waddr || id_stall_raddr1 || id_stall_raddr2 || id_stall_waddr ||
@ -805,13 +740,11 @@ class rocketCtrl extends Component
id_mem_val && !(io.dmem.req.ready && io.dtlb_rdy) || id_mem_val && !(io.dmem.req.ready && io.dtlb_rdy) ||
(id_sync === SYNC_D || id_sync === SYNC_I) && !io.dmem.req.ready || (id_sync === SYNC_D || id_sync === SYNC_I) && !io.dmem.req.ready ||
vec_stalld vec_stalld
ctrl_killd := !io.imem.resp.valid || take_pc || ctrl_stalld || id_interrupt
io.dpath.killd := take_pc || ctrl_stalld && !id_interrupt
io.dpath.flush_inst := wb_reg_flush_inst; io.dpath.flush_inst := wb_reg_flush_inst;
io.dpath.stalld := !ctrl_killd && ctrl_stalld; io.imem.resp.ready := take_pc || !ctrl_stalld
io.dpath.killd := ctrl_killd || ctrl_stalld
io.dpath.killx := kill_ex;
io.dpath.killm := killm_common
io.imem.resp.ready := killd_common || !ctrl_stalld
io.imem.req.bits.invalidate := wb_reg_flush_inst io.imem.req.bits.invalidate := wb_reg_flush_inst
io.dpath.mem_load := mem_reg_mem_val && mem_reg_wen io.dpath.mem_load := mem_reg_mem_val && mem_reg_wen
@ -836,18 +769,17 @@ class rocketCtrl extends Component
io.dpath.sel_wa := id_sel_wa.toBool; io.dpath.sel_wa := id_sel_wa.toBool;
io.dpath.sel_wb := id_sel_wb.toUFix io.dpath.sel_wb := id_sel_wb.toUFix
io.dpath.pcr := wb_reg_pcr.toUFix io.dpath.pcr := wb_reg_pcr.toUFix
io.dpath.id_eret := id_eret.toBool;
io.dpath.wb_eret := wb_reg_eret; io.dpath.wb_eret := wb_reg_eret;
io.dpath.ex_mem_type := ex_reg_mem_type io.dpath.ex_mem_type := ex_reg_mem_type
io.fpu.valid := !io.dpath.killd && id_fp_val io.fpu.valid := !ctrl_killd && id_fp_val
io.fpu.killx := kill_ex io.fpu.killx := ctrl_killx
io.fpu.killm := killm_common io.fpu.killm := killm_common
io.dtlb_val := ex_reg_mem_val io.dtlb_val := ex_reg_mem_val
io.dtlb_kill := mem_reg_kill io.dtlb_kill := !mem_reg_valid
io.dmem.req.valid := ex_reg_mem_val io.dmem.req.valid := ex_reg_mem_val
io.dmem.req.bits.kill := killm_common || io.dtlb_miss io.dmem.req.bits.kill := killm_common || mem_xcpt || io.dtlb_miss
io.dmem.req.bits.cmd := ex_reg_mem_cmd io.dmem.req.bits.cmd := ex_reg_mem_cmd
io.dmem.req.bits.typ := ex_reg_mem_type io.dmem.req.bits.typ := ex_reg_mem_type
} }

2
rocket/src/main/scala/divider.scala
View File

@ -15,7 +15,7 @@ class rocketDivider(earlyOut: Boolean = false) extends Component {
val divby0 = Reg() { Bool() }; val divby0 = Reg() { Bool() };
val neg_quo = Reg() { Bool() }; val neg_quo = Reg() { Bool() };
val neg_rem = Reg() { Bool() }; val neg_rem = Reg() { Bool() };
val reg_tag = Reg() { Bits() }; val reg_tag = Reg() { UFix() };
val rem = Reg() { Bool() }; val rem = Reg() { Bool() };
val half = Reg() { Bool() }; val half = Reg() { Bool() };

117
rocket/src/main/scala/dpath.scala
View File

@ -32,8 +32,6 @@ class rocketDpath(implicit conf: RocketConfiguration) extends Component
val alu = new ALU val alu = new ALU
val ex_alu_out = alu.io.out; val ex_alu_out = alu.io.out;
val ex_alu_adder_out = alu.io.adder_out; val ex_alu_adder_out = alu.io.adder_out;
val rfile = new rocketDpathRegfile();
// execute definitions // execute definitions
val ex_reg_pc = Reg() { UFix() }; val ex_reg_pc = Reg() { UFix() };
@ -48,6 +46,7 @@ class rocketDpath(implicit conf: RocketConfiguration) extends Component
val ex_reg_ctrl_fn_alu = Reg() { UFix() }; val ex_reg_ctrl_fn_alu = Reg() { UFix() };
val ex_reg_ctrl_sel_wb = Reg() { UFix() }; val ex_reg_ctrl_sel_wb = Reg() { UFix() };
val ex_wdata = Bits() val ex_wdata = Bits()
val ex_reg_kill = Reg() { Bool() }
// memory definitions // memory definitions
val mem_reg_pc = Reg() { UFix() }; val mem_reg_pc = Reg() { UFix() };
@ -57,6 +56,7 @@ class rocketDpath(implicit conf: RocketConfiguration) extends Component
val mem_reg_wdata = Reg() { Bits() }; val mem_reg_wdata = Reg() { Bits() };
val mem_reg_raddr1 = Reg() { UFix() }; val mem_reg_raddr1 = Reg() { UFix() };
val mem_reg_raddr2 = Reg() { UFix() }; val mem_reg_raddr2 = Reg() { UFix() };
val mem_reg_kill = Reg() { Bool() }
// writeback definitions // writeback definitions
val wb_reg_pc = Reg() { UFix() }; val wb_reg_pc = Reg() { UFix() };
@ -98,24 +98,14 @@ class rocketDpath(implicit conf: RocketConfiguration) extends Component
val id_pc = io.imem.resp.bits.pc val id_pc = io.imem.resp.bits.pc
debug(id_inst) debug(id_inst)
debug(id_pc) debug(id_pc)
val regfile_ = Mem(31){Bits(width = 64)}
def readRF(a: UFix) = Mux(a === UFix(0), Bits(0), regfile_(~a))
def writeRF(a: UFix, d: Bits) = regfile_(~a) := d
val id_raddr1 = id_inst(26,22).toUFix; val id_raddr1 = id_inst(26,22).toUFix;
val id_raddr2 = id_inst(21,17).toUFix; val id_raddr2 = id_inst(21,17).toUFix;
// regfile read
rfile.io.r0.en <> io.ctrl.ren2;
rfile.io.r0.addr := id_raddr2;
val id_rdata2 = rfile.io.r0.data;
rfile.io.r1.en <> io.ctrl.ren1;
rfile.io.r1.addr := id_raddr1;
val id_rdata1 = rfile.io.r1.data;
// destination register selection
val id_waddr =
Mux(io.ctrl.sel_wa === WA_RD, id_inst(31,27).toUFix,
RA); // WA_RA
// bypass muxes // bypass muxes
val id_rs1_dmem_bypass = val id_rs1_dmem_bypass =
Mux(io.ctrl.ex_wen && id_raddr1 === ex_reg_waddr, Bool(false), Mux(io.ctrl.ex_wen && id_raddr1 === ex_reg_waddr, Bool(false),
@ -125,7 +115,7 @@ class rocketDpath(implicit conf: RocketConfiguration) extends Component
Mux(io.ctrl.ex_wen && id_raddr1 === ex_reg_waddr, ex_wdata, Mux(io.ctrl.ex_wen && id_raddr1 === ex_reg_waddr, ex_wdata,
Mux(io.ctrl.mem_wen && id_raddr1 === mem_reg_waddr, mem_reg_wdata, Mux(io.ctrl.mem_wen && id_raddr1 === mem_reg_waddr, mem_reg_wdata,
Mux((io.ctrl.wb_wen || wb_reg_ll_wb) && id_raddr1 === wb_reg_waddr, wb_wdata, Mux((io.ctrl.wb_wen || wb_reg_ll_wb) && id_raddr1 === wb_reg_waddr, wb_wdata,
id_rdata1))) readRF(id_raddr1))))
val id_rs2_dmem_bypass = val id_rs2_dmem_bypass =
Mux(io.ctrl.ex_wen && id_raddr2 === ex_reg_waddr, Bool(false), Mux(io.ctrl.ex_wen && id_raddr2 === ex_reg_waddr, Bool(false),
@ -135,7 +125,7 @@ class rocketDpath(implicit conf: RocketConfiguration) extends Component
Mux(io.ctrl.ex_wen && id_raddr2 === ex_reg_waddr, ex_wdata, Mux(io.ctrl.ex_wen && id_raddr2 === ex_reg_waddr, ex_wdata,
Mux(io.ctrl.mem_wen && id_raddr2 === mem_reg_waddr, mem_reg_wdata, Mux(io.ctrl.mem_wen && id_raddr2 === mem_reg_waddr, mem_reg_wdata,
Mux((io.ctrl.wb_wen || wb_reg_ll_wb) && id_raddr2 === wb_reg_waddr, wb_wdata, Mux((io.ctrl.wb_wen || wb_reg_ll_wb) && id_raddr2 === wb_reg_waddr, wb_wdata,
id_rdata2))) readRF(id_raddr2))))
// immediate generation // immediate generation
val id_imm_bj = io.ctrl.sel_alu2 === A2_BTYPE || io.ctrl.sel_alu2 === A2_JTYPE val id_imm_bj = io.ctrl.sel_alu2 === A2_BTYPE || io.ctrl.sel_alu2 === A2_JTYPE
@ -160,17 +150,20 @@ class rocketDpath(implicit conf: RocketConfiguration) extends Component
io.fpu.inst := id_inst io.fpu.inst := id_inst
// execute stage // execute stage
ex_reg_pc := id_pc ex_reg_kill := io.ctrl.killd
ex_reg_inst := id_inst when (!io.ctrl.killd) {
ex_reg_raddr1 := id_raddr1 ex_reg_pc := id_pc
ex_reg_raddr2 := id_raddr2; ex_reg_inst := id_inst
ex_reg_op2 := id_op2; ex_reg_raddr1 := id_raddr1
ex_reg_rs2 := id_rs2; ex_reg_raddr2 := id_raddr2
ex_reg_rs1 := id_rs1; ex_reg_op2 := id_op2
ex_reg_waddr := id_waddr; ex_reg_waddr := Mux(io.ctrl.sel_wa === WA_RD, id_inst(31,27).toUFix, RA)
ex_reg_ctrl_fn_dw := io.ctrl.fn_dw.toUFix; ex_reg_ctrl_fn_dw := io.ctrl.fn_dw.toUFix
ex_reg_ctrl_fn_alu := io.ctrl.fn_alu; ex_reg_ctrl_fn_alu := io.ctrl.fn_alu
ex_reg_ctrl_sel_wb := io.ctrl.sel_wb; ex_reg_ctrl_sel_wb := io.ctrl.sel_wb
when (io.ctrl.ren1) { ex_reg_rs1 := id_rs1 }
when (io.ctrl.ren2) { ex_reg_rs2 := id_rs2 }
}
val ex_rs1 = Mux(Reg(id_rs1_dmem_bypass), wb_reg_dmem_wdata, ex_reg_rs1) val ex_rs1 = Mux(Reg(id_rs1_dmem_bypass), wb_reg_dmem_wdata, ex_reg_rs1)
val ex_rs2 = Mux(Reg(id_rs2_dmem_bypass), wb_reg_dmem_wdata, ex_reg_rs2) val ex_rs2 = Mux(Reg(id_rs2_dmem_bypass), wb_reg_dmem_wdata, ex_reg_rs2)
@ -188,7 +181,7 @@ class rocketDpath(implicit conf: RocketConfiguration) extends Component
div.io.req.valid := io.ctrl.div_val div.io.req.valid := io.ctrl.div_val
div.io.req.bits.fn := Cat(ex_reg_ctrl_fn_dw, io.ctrl.div_fn) div.io.req.bits.fn := Cat(ex_reg_ctrl_fn_dw, io.ctrl.div_fn)
div.io.req.bits.in0 := ex_rs1 div.io.req.bits.in0 := ex_rs1
div.io.req.bits.in1 := ex_rs2 div.io.req.bits.in1 := ex_op2
div.io.req_tag := ex_reg_waddr div.io.req_tag := ex_reg_waddr
div.io.req_kill := io.ctrl.div_kill div.io.req_kill := io.ctrl.div_kill
div.io.resp_rdy := !dmem_resp_replay div.io.resp_rdy := !dmem_resp_replay
@ -207,7 +200,7 @@ class rocketDpath(implicit conf: RocketConfiguration) extends Component
mul_io.req.valid := io.ctrl.mul_val mul_io.req.valid := io.ctrl.mul_val
mul_io.req.bits.fn := Cat(ex_reg_ctrl_fn_dw, io.ctrl.mul_fn) mul_io.req.bits.fn := Cat(ex_reg_ctrl_fn_dw, io.ctrl.mul_fn)
mul_io.req.bits.in0 := ex_rs1 mul_io.req.bits.in0 := ex_rs1
mul_io.req.bits.in1 := ex_rs2 mul_io.req.bits.in1 := ex_op2
mul_io.req_tag := ex_reg_waddr mul_io.req_tag := ex_reg_waddr
mul_io.req_kill := io.ctrl.mul_kill mul_io.req_kill := io.ctrl.mul_kill
mul_io.resp_rdy := !dmem_resp_replay && !div.io.resp_val mul_io.resp_rdy := !dmem_resp_replay && !div.io.resp_val
@ -264,13 +257,16 @@ class rocketDpath(implicit conf: RocketConfiguration) extends Component
storegen.io.din := ex_rs2 storegen.io.din := ex_rs2
// memory stage // memory stage
mem_reg_pc := ex_reg_pc; mem_reg_kill := ex_reg_kill
mem_reg_inst := ex_reg_inst when (!ex_reg_kill) {
mem_reg_rs2 := storegen.io.dout mem_reg_pc := ex_reg_pc
mem_reg_waddr := ex_reg_waddr; mem_reg_inst := ex_reg_inst
mem_reg_wdata := ex_wdata; mem_reg_rs2 := storegen.io.dout
mem_reg_raddr1 := ex_reg_raddr1 mem_reg_waddr := ex_reg_waddr
mem_reg_raddr2 := ex_reg_raddr2; mem_reg_wdata := ex_wdata
mem_reg_raddr1 := ex_reg_raddr1
mem_reg_raddr2 := ex_reg_raddr2
}
// for load/use hazard detection (load byte/halfword) // for load/use hazard detection (load byte/halfword)
io.ctrl.mem_waddr := mem_reg_waddr; io.ctrl.mem_waddr := mem_reg_waddr;
@ -288,12 +284,9 @@ class rocketDpath(implicit conf: RocketConfiguration) extends Component
val mem_ll_waddr = Mux(dmem_resp_replay, dmem_resp_waddr, val mem_ll_waddr = Mux(dmem_resp_replay, dmem_resp_waddr,
Mux(div.io.resp_val, div.io.resp_tag, Mux(div.io.resp_val, div.io.resp_tag,
Mux(mul_io.resp_val, mul_io.resp_tag, mul_io.resp_tag))
mem_reg_waddr))).toUFix
val mem_ll_wdata = Mux(div.io.resp_val, div.io.resp_bits, val mem_ll_wdata = Mux(div.io.resp_val, div.io.resp_bits,
Mux(mul_io.resp_val, mul_io.resp_bits, mul_io.resp_bits)
Mux(io.ctrl.mem_fp_val && io.ctrl.mem_wen, io.fpu.toint_data,
mem_reg_wdata)))
val mem_ll_wb = dmem_resp_replay || div.io.resp_val || mul_io.resp_val val mem_ll_wb = dmem_resp_replay || div.io.resp_val || mul_io.resp_val
io.fpu.dmem_resp_val := io.dmem.resp.valid && dmem_resp_fpu io.fpu.dmem_resp_val := io.dmem.resp.valid && dmem_resp_fpu
@ -302,17 +295,25 @@ class rocketDpath(implicit conf: RocketConfiguration) extends Component
io.fpu.dmem_resp_tag := dmem_resp_waddr io.fpu.dmem_resp_tag := dmem_resp_waddr
// writeback stage // writeback stage
wb_reg_pc := mem_reg_pc; when (io.ctrl.mem_load) {
wb_reg_inst := mem_reg_inst wb_reg_dmem_wdata := io.dmem.resp.bits.data
wb_reg_ll_wb := mem_ll_wb }
wb_reg_rs2 := mem_reg_rs2 when (!mem_reg_kill) {
wb_reg_waddr := mem_ll_waddr wb_reg_pc := mem_reg_pc
wb_reg_wdata := mem_ll_wdata wb_reg_inst := mem_reg_inst
wb_reg_dmem_wdata := io.dmem.resp.bits.data wb_reg_rs2 := mem_reg_rs2
wb_reg_vec_waddr := mem_reg_waddr wb_reg_vec_waddr := mem_reg_waddr
wb_reg_vec_wdata := mem_reg_wdata wb_reg_vec_wdata := mem_reg_wdata
wb_reg_raddr1 := mem_reg_raddr1 wb_reg_raddr1 := mem_reg_raddr1
wb_reg_raddr2 := mem_reg_raddr2; wb_reg_raddr2 := mem_reg_raddr2
wb_reg_waddr := mem_reg_waddr
wb_reg_wdata := Mux(io.ctrl.mem_fp_val && io.ctrl.mem_wen, io.fpu.toint_data, mem_reg_wdata)
}
wb_reg_ll_wb := mem_ll_wb
when (mem_ll_wb) {
wb_reg_waddr := mem_ll_waddr
wb_reg_wdata := mem_ll_wdata
}
// regfile write // regfile write
val wb_src_dmem = Reg(io.ctrl.mem_load) && io.ctrl.wb_valid || r_dmem_resp_replay val wb_src_dmem = Reg(io.ctrl.mem_load) && io.ctrl.wb_valid || r_dmem_resp_replay
@ -356,9 +357,11 @@ class rocketDpath(implicit conf: RocketConfiguration) extends Component
wb_reg_wdata) wb_reg_wdata)
} }
rfile.io.w0.addr := wb_reg_waddr val rf_wen = io.ctrl.wb_wen || wb_reg_ll_wb
rfile.io.w0.en := io.ctrl.wb_wen || wb_reg_ll_wb val rf_waddr = wb_reg_waddr
rfile.io.w0.data := Mux(io.ctrl.pcr != PCR_N && io.ctrl.wb_wen, pcr.io.r.data, wb_wdata) val rf_wdata = Mux(io.ctrl.wb_wen && io.ctrl.pcr != PCR_N, pcr.io.r.data, wb_wdata)
List(rf_wen, rf_waddr, rf_wdata).map(debug _)
when (rf_wen) { writeRF(rf_waddr, rf_wdata) }
io.ctrl.wb_waddr := wb_reg_waddr io.ctrl.wb_waddr := wb_reg_waddr
io.ctrl.mem_wb := dmem_resp_replay; io.ctrl.mem_wb := dmem_resp_replay;

39
rocket/src/main/scala/dpath_util.scala
View File

@ -56,8 +56,8 @@ class rocketDpathBTB(entries: Int) extends Component
class ioDpathPCR(implicit conf: RocketConfiguration) extends Bundle class ioDpathPCR(implicit conf: RocketConfiguration) extends Bundle
{ {
val host = new ioHTIF(conf.ntiles) val host = new ioHTIF(conf.ntiles)
val r = new ioReadPort(); val r = new ioReadPort(32, 64)
val w = new ioWritePort(); val w = new ioWritePort(32, 64)
val status = Bits(OUTPUT, 32); val status = Bits(OUTPUT, 32);
val ptbr = UFix(OUTPUT, PADDR_BITS); val ptbr = UFix(OUTPUT, PADDR_BITS);
@ -228,33 +228,18 @@ class rocketDpathPCR(implicit conf: RocketConfiguration) extends Component
} }
} }
class ioReadPort extends Bundle() class ioReadPort(d: Int, w: Int) extends Bundle
{ {
val addr = UFix(INPUT, 5); val addr = UFix(INPUT, log2Up(d))
val en = Bool(INPUT); val en = Bool(INPUT)
val data = Bits(OUTPUT, 64); val data = Bits(OUTPUT, w)
override def clone = new ioReadPort(d, w).asInstanceOf[this.type]
} }
class ioWritePort extends Bundle() class ioWritePort(d: Int, w: Int) extends Bundle
{ {
val addr = UFix(INPUT, 5); val addr = UFix(INPUT, log2Up(d))
val en = Bool(INPUT); val en = Bool(INPUT)
val data = Bits(INPUT, 64); val data = Bits(INPUT, w)
} override def clone = new ioWritePort(d, w).asInstanceOf[this.type]
class ioRegfile extends Bundle()
{
val r0 = new ioReadPort();
val r1 = new ioReadPort();
val w0 = new ioWritePort();
}
class rocketDpathRegfile extends Component
{
override val io = new ioRegfile();
val regfile = Mem(32){ Bits(width=64) }
when (io.w0.en) { regfile(io.w0.addr) := io.w0.data }
io.r0.data := Mux((io.r0.addr === UFix(0, 5)) || !io.r0.en, Bits(0, 64), regfile(io.r0.addr));
io.r1.data := Mux((io.r1.addr === UFix(0, 5)) || !io.r1.en, Bits(0, 64), regfile(io.r1.addr));
} }

651
rocket/src/main/scala/fpu.scala
View File

@ -4,6 +4,7 @@ import Chisel._
import Node._ import Node._
import Constants._ import Constants._
import Instructions._ import Instructions._
import Util._
object rocketFPConstants object rocketFPConstants
{ {
@ -46,11 +47,10 @@ object rocketFPConstants
} }
import rocketFPConstants._ import rocketFPConstants._
class rocketFPUCtrlSigs extends Bundle class FPUCtrlSigs extends Bundle
{ {
val cmd = Bits(width = FCMD_WIDTH) val cmd = Bits(width = FCMD_WIDTH)
val wen = Bool() val wen = Bool()
val sboard = Bool()
val ren1 = Bool() val ren1 = Bool()
val ren2 = Bool() val ren2 = Bool()
val ren3 = Bool() val ren3 = Bool()
@ -68,78 +68,77 @@ class rocketFPUDecoder extends Component
{ {
val io = new Bundle { val io = new Bundle {
val inst = Bits(INPUT, 32) val inst = Bits(INPUT, 32)
val sigs = new rocketFPUCtrlSigs().asOutput val sigs = new FPUCtrlSigs().asOutput
} }
val N = Bool(false) val N = Bool(false)
val Y = Bool(true) val Y = Bool(true)
val X = Bool(false) val X = Bool(false)
val decoder = DecodeLogic(io.inst, val decoder = DecodeLogic(io.inst,
List (FCMD_X, X,X,X,X,X,X,X,X,X,X,X,X,X), List (FCMD_X, X,X,X,X,X,X,X,X,X,X,X),
Array(FLW -> List(FCMD_LOAD, Y,N,N,N,N,Y,N,N,N,N,N,N,N), Array(FLW -> List(FCMD_LOAD, Y,N,N,N,Y,N,N,N,N,N,N),
FLD -> List(FCMD_LOAD, Y,N,N,N,N,N,N,N,N,N,N,N,N), FLD -> List(FCMD_LOAD, Y,N,N,N,N,N,N,N,N,N,N),
FSW -> List(FCMD_STORE, N,N,N,Y,N,Y,N,N,N,N,Y,N,N), FSW -> List(FCMD_STORE, N,N,Y,N,Y,N,Y,N,N,N,N),
FSD -> List(FCMD_STORE, N,N,N,Y,N,N,N,N,N,N,Y,N,N), FSD -> List(FCMD_STORE, N,N,Y,N,N,N,Y,N,N,N,N),
MXTF_S -> List(FCMD_MXTF, Y,N,N,N,N,Y,Y,N,Y,N,N,N,N), MXTF_S -> List(FCMD_MXTF, Y,N,N,N,Y,Y,N,N,N,N,N),
MXTF_D -> List(FCMD_MXTF, Y,N,N,N,N,N,Y,N,Y,N,N,N,N), MXTF_D -> List(FCMD_MXTF, Y,N,N,N,N,Y,N,N,N,N,N),
FCVT_S_W -> List(FCMD_CVT_FMT_W, Y,N,N,N,N,Y,Y,N,Y,N,N,N,N), FCVT_S_W -> List(FCMD_CVT_FMT_W, Y,N,N,N,Y,Y,N,N,N,N,N),
FCVT_S_WU-> List(FCMD_CVT_FMT_WU,Y,N,N,N,N,Y,Y,N,Y,N,N,N,N), FCVT_S_WU-> List(FCMD_CVT_FMT_WU,Y,N,N,N,Y,Y,N,N,N,N,N),
FCVT_S_L -> List(FCMD_CVT_FMT_L, Y,N,N,N,N,Y,Y,N,Y,N,N,N,N), FCVT_S_L -> List(FCMD_CVT_FMT_L, Y,N,N,N,Y,Y,N,N,N,N,N),
FCVT_S_LU-> List(FCMD_CVT_FMT_LU,Y,N,N,N,N,Y,Y,N,Y,N,N,N,N), FCVT_S_LU-> List(FCMD_CVT_FMT_LU,Y,N,N,N,Y,Y,N,N,N,N,N),
FCVT_D_W -> List(FCMD_CVT_FMT_W, Y,N,N,N,N,N,Y,N,Y,N,N,N,N), FCVT_D_W -> List(FCMD_CVT_FMT_W, Y,N,N,N,N,Y,N,N,N,N,N),
FCVT_D_WU-> List(FCMD_CVT_FMT_WU,Y,N,N,N,N,N,Y,N,Y,N,N,N,N), FCVT_D_WU-> List(FCMD_CVT_FMT_WU,Y,N,N,N,N,Y,N,N,N,N,N),
FCVT_D_L -> List(FCMD_CVT_FMT_L, Y,N,N,N,N,N,Y,N,Y,N,N,N,N), FCVT_D_L -> List(FCMD_CVT_FMT_L, Y,N,N,N,N,Y,N,N,N,N,N),
FCVT_D_LU-> List(FCMD_CVT_FMT_LU,Y,N,N,N,N,N,Y,N,Y,N,N,N,N), FCVT_D_LU-> List(FCMD_CVT_FMT_LU,Y,N,N,N,N,Y,N,N,N,N,N),
MFTX_S -> List(FCMD_MFTX, N,N,Y,N,N,Y,N,Y,N,N,N,N,N), MFTX_S -> List(FCMD_MFTX, N,Y,N,N,Y,N,Y,N,N,N,N),
MFTX_D -> List(FCMD_MFTX, N,N,Y,N,N,N,N,Y,N,N,N,N,N), MFTX_D -> List(FCMD_MFTX, N,Y,N,N,N,N,Y,N,N,N,N),
FCVT_W_S -> List(FCMD_CVT_W_FMT, N,N,Y,N,N,Y,N,Y,N,N,N,N,N), FCVT_W_S -> List(FCMD_CVT_W_FMT, N,Y,N,N,Y,N,Y,N,N,N,N),
FCVT_WU_S-> List(FCMD_CVT_WU_FMT,N,N,Y,N,N,Y,N,Y,N,N,N,N,N), FCVT_WU_S-> List(FCMD_CVT_WU_FMT,N,Y,N,N,Y,N,Y,N,N,N,N),
FCVT_L_S -> List(FCMD_CVT_L_FMT, N,N,Y,N,N,Y,N,Y,N,N,N,N,N), FCVT_L_S -> List(FCMD_CVT_L_FMT, N,Y,N,N,Y,N,Y,N,N,N,N),
FCVT_LU_S-> List(FCMD_CVT_LU_FMT,N,N,Y,N,N,Y,N,Y,N,N,N,N,N), FCVT_LU_S-> List(FCMD_CVT_LU_FMT,N,Y,N,N,Y,N,Y,N,N,N,N),
FCVT_W_D -> List(FCMD_CVT_W_FMT, N,N,Y,N,N,N,N,Y,N,N,N,N,N), FCVT_W_D -> List(FCMD_CVT_W_FMT, N,Y,N,N,N,N,Y,N,N,N,N),
FCVT_WU_D-> List(FCMD_CVT_WU_FMT,N,N,Y,N,N,N,N,Y,N,N,N,N,N), FCVT_WU_D-> List(FCMD_CVT_WU_FMT,N,Y,N,N,N,N,Y,N,N,N,N),
FCVT_L_D -> List(FCMD_CVT_L_FMT, N,N,Y,N,N,N,N,Y,N,N,N,N,N), FCVT_L_D -> List(FCMD_CVT_L_FMT, N,Y,N,N,N,N,Y,N,N,N,N),
FCVT_LU_D-> List(FCMD_CVT_LU_FMT,N,N,Y,N,N,N,N,Y,N,N,N,N,N), FCVT_LU_D-> List(FCMD_CVT_LU_FMT,N,Y,N,N,N,N,Y,N,N,N,N),
FCVT_S_D -> List(FCMD_CVT_FMT_D, Y,N,Y,N,N,Y,N,N,Y,N,N,N,N), FCVT_S_D -> List(FCMD_CVT_FMT_D, Y,Y,N,N,Y,N,N,Y,N,N,N),
FCVT_D_S -> List(FCMD_CVT_FMT_S, Y,N,Y,N,N,N,N,N,Y,N,N,N,N), FCVT_D_S -> List(FCMD_CVT_FMT_S, Y,Y,N,N,N,N,N,Y,N,N,N),
FEQ_S -> List(FCMD_EQ, N,N,Y,Y,N,Y,N,Y,N,N,N,N,N), FEQ_S -> List(FCMD_EQ, N,Y,Y,N,Y,N,Y,N,N,N,N),
FLT_S -> List(FCMD_LT, N,N,Y,Y,N,Y,N,Y,N,N,N,N,N), FLT_S -> List(FCMD_LT, N,Y,Y,N,Y,N,Y,N,N,N,N),
FLE_S -> List(FCMD_LE, N,N,Y,Y,N,Y,N,Y,N,N,N,N,N), FLE_S -> List(FCMD_LE, N,Y,Y,N,Y,N,Y,N,N,N,N),
FEQ_D -> List(FCMD_EQ, N,N,Y,Y,N,N,N,Y,N,N,N,N,N), FEQ_D -> List(FCMD_EQ, N,Y,Y,N,N,N,Y,N,N,N,N),
FLT_D -> List(FCMD_LT, N,N,Y,Y,N,N,N,Y,N,N,N,N,N), FLT_D -> List(FCMD_LT, N,Y,Y,N,N,N,Y,N,N,N,N),
FLE_D -> List(FCMD_LE, N,N,Y,Y,N,N,N,Y,N,N,N,N,N), FLE_D -> List(FCMD_LE, N,Y,Y,N,N,N,Y,N,N,N,N),
MTFSR -> List(FCMD_MTFSR, N,N,N,N,N,Y,N,Y,N,N,N,Y,Y), MTFSR -> List(FCMD_MTFSR, N,N,N,N,Y,N,Y,N,N,Y,Y),
MFFSR -> List(FCMD_MFFSR, N,N,N,N,N,Y,N,Y,N,N,N,Y,N), MFFSR -> List(FCMD_MFFSR, N,N,N,N,Y,N,Y,N,N,Y,N),
FSGNJ_S -> List(FCMD_SGNJ, Y,N,Y,Y,N,Y,N,N,Y,N,N,N,N), FSGNJ_S -> List(FCMD_SGNJ, Y,Y,Y,N,Y,N,N,Y,N,N,N),
FSGNJN_S -> List(FCMD_SGNJN, Y,N,Y,Y,N,Y,N,N,Y,N,N,N,N), FSGNJN_S -> List(FCMD_SGNJN, Y,Y,Y,N,Y,N,N,Y,N,N,N),
FSGNJX_S -> List(FCMD_SGNJX, Y,N,Y,Y,N,Y,N,N,Y,N,N,N,N), FSGNJX_S -> List(FCMD_SGNJX, Y,Y,Y,N,Y,N,N,Y,N,N,N),
FSGNJ_D -> List(FCMD_SGNJ, Y,N,Y,Y,N,N,N,N,Y,N,N,N,N), FSGNJ_D -> List(FCMD_SGNJ, Y,Y,Y,N,N,N,N,Y,N,N,N),
FSGNJN_D -> List(FCMD_SGNJN, Y,N,Y,Y,N,N,N,N,Y,N,N,N,N), FSGNJN_D -> List(FCMD_SGNJN, Y,Y,Y,N,N,N,N,Y,N,N,N),
FSGNJX_D -> List(FCMD_SGNJX, Y,N,Y,Y,N,N,N,N,Y,N,N,N,N), FSGNJX_D -> List(FCMD_SGNJX, Y,Y,Y,N,N,N,N,Y,N,N,N),
FMIN_S -> List(FCMD_MIN, Y,N,Y,Y,N,Y,N,N,Y,N,N,N,N), FMIN_S -> List(FCMD_MIN, Y,Y,Y,N,Y,N,Y,Y,N,N,N),
FMAX_S -> List(FCMD_MAX, Y,N,Y,Y,N,Y,N,N,Y,N,N,N,N), FMAX_S -> List(FCMD_MAX, Y,Y,Y,N,Y,N,Y,Y,N,N,N),
FMIN_D -> List(FCMD_MIN, Y,N,Y,Y,N,N,N,N,Y,N,N,N,N), FMIN_D -> List(FCMD_MIN, Y,Y,Y,N,N,N,Y,Y,N,N,N),
FMAX_D -> List(FCMD_MAX, Y,N,Y,Y,N,N,N,N,Y,N,N,N,N), FMAX_D -> List(FCMD_MAX, Y,Y,Y,N,N,N,Y,Y,N,N,N),
FADD_S -> List(FCMD_ADD, Y,Y,Y,Y,N,Y,N,N,N,Y,N,N,N), FADD_S -> List(FCMD_ADD, Y,Y,Y,N,Y,N,N,N,Y,N,N),
FSUB_S -> List(FCMD_SUB, Y,Y,Y,Y,N,Y,N,N,N,Y,N,N,N), FSUB_S -> List(FCMD_SUB, Y,Y,Y,N,Y,N,N,N,Y,N,N),
FMUL_S -> List(FCMD_MUL, Y,Y,Y,Y,N,Y,N,N,N,Y,N,N,N), FMUL_S -> List(FCMD_MUL, Y,Y,Y,N,Y,N,N,N,Y,N,N),
FADD_D -> List(FCMD_ADD, Y,Y,Y,Y,N,N,N,N,N,Y,N,N,N), FADD_D -> List(FCMD_ADD, Y,Y,Y,N,N,N,N,N,Y,N,N),
FSUB_D -> List(FCMD_SUB, Y,Y,Y,Y,N,N,N,N,N,Y,N,N,N), FSUB_D -> List(FCMD_SUB, Y,Y,Y,N,N,N,N,N,Y,N,N),
FMUL_D -> List(FCMD_MUL, Y,Y,Y,Y,N,N,N,N,N,Y,N,N,N), FMUL_D -> List(FCMD_MUL, Y,Y,Y,N,N,N,N,N,Y,N,N),
FMADD_S -> List(FCMD_MADD, Y,Y,Y,Y,Y,Y,N,N,N,Y,N,N,N), FMADD_S -> List(FCMD_MADD, Y,Y,Y,Y,Y,N,N,N,Y,N,N),
FMSUB_S -> List(FCMD_MSUB, Y,Y,Y,Y,Y,Y,N,N,N,Y,N,N,N), FMSUB_S -> List(FCMD_MSUB, Y,Y,Y,Y,Y,N,N,N,Y,N,N),
FNMADD_S -> List(FCMD_NMADD, Y,Y,Y,Y,Y,Y,N,N,N,Y,N,N,N), FNMADD_S -> List(FCMD_NMADD, Y,Y,Y,Y,Y,N,N,N,Y,N,N),
FNMSUB_S -> List(FCMD_NMSUB, Y,Y,Y,Y,Y,Y,N,N,N,Y,N,N,N), FNMSUB_S -> List(FCMD_NMSUB, Y,Y,Y,Y,Y,N,N,N,Y,N,N),
FMADD_D -> List(FCMD_MADD, Y,Y,Y,Y,Y,N,N,N,N,Y,N,N,N), FMADD_D -> List(FCMD_MADD, Y,Y,Y,Y,N,N,N,N,Y,N,N),
FMSUB_D -> List(FCMD_MSUB, Y,Y,Y,Y,Y,N,N,N,N,Y,N,N,N), FMSUB_D -> List(FCMD_MSUB, Y,Y,Y,Y,N,N,N,N,Y,N,N),
FNMADD_D -> List(FCMD_NMADD, Y,Y,Y,Y,Y,N,N,N,N,Y,N,N,N), FNMADD_D -> List(FCMD_NMADD, Y,Y,Y,Y,N,N,N,N,Y,N,N),
FNMSUB_D -> List(FCMD_NMSUB, Y,Y,Y,Y,Y,N,N,N,N,Y,N,N,N) FNMSUB_D -> List(FCMD_NMSUB, Y,Y,Y,Y,N,N,N,N,Y,N,N)
)) ))
val cmd :: wen :: sboard :: ren1 :: ren2 :: ren3 :: single :: fromint :: toint :: fastpipe :: fma :: store :: rdfsr :: wrfsr :: Nil = decoder val cmd :: wen :: ren1 :: ren2 :: ren3 :: single :: fromint :: toint :: fastpipe :: fma :: rdfsr :: wrfsr :: Nil = decoder
io.sigs.cmd := cmd io.sigs.cmd := cmd
io.sigs.wen := wen.toBool io.sigs.wen := wen.toBool
io.sigs.sboard := sboard.toBool
io.sigs.ren1 := ren1.toBool io.sigs.ren1 := ren1.toBool
io.sigs.ren2 := ren2.toBool io.sigs.ren2 := ren2.toBool
io.sigs.ren3 := ren3.toBool io.sigs.ren3 := ren3.toBool
@ -148,7 +147,6 @@ class rocketFPUDecoder extends Component
io.sigs.toint := toint.toBool io.sigs.toint := toint.toBool
io.sigs.fastpipe := fastpipe.toBool io.sigs.fastpipe := fastpipe.toBool
io.sigs.fma := fma.toBool io.sigs.fma := fma.toBool
io.sigs.store := store.toBool
io.sigs.rdfsr := rdfsr.toBool io.sigs.rdfsr := rdfsr.toBool
io.sigs.wrfsr := wrfsr.toBool io.sigs.wrfsr := wrfsr.toBool
} }
@ -172,169 +170,201 @@ class ioCtrlFPU extends Bundle {
val illegal_rm = Bool(INPUT) val illegal_rm = Bool(INPUT)
val killx = Bool(OUTPUT) val killx = Bool(OUTPUT)
val killm = Bool(OUTPUT) val killm = Bool(OUTPUT)
val dec = new rocketFPUCtrlSigs().asInput val dec = new FPUCtrlSigs().asInput
val sboard_set = Bool(INPUT)
val sboard_clr = Bool(INPUT) val sboard_clr = Bool(INPUT)
val sboard_clra = UFix(INPUT, 5) val sboard_clra = UFix(INPUT, 5)
} }
class rocketFPIntUnit extends Component object RegEn
{ {
val io = new Bundle { def apply[T <: Data](data: T, en: Bool) = {
val single = Bool(INPUT) val r = Reg() { data.clone }
val cmd = Bits(INPUT, FCMD_WIDTH) when (en) { r := data }
val rm = Bits(INPUT, 3) r
val fsr = Bits(INPUT, FSR_WIDTH)
val in1 = Bits(INPUT, 65)
val in2 = Bits(INPUT, 65)
val lt_s = Bool(OUTPUT)
val lt_d = Bool(OUTPUT)
val store_data = Bits(OUTPUT, 64)
val toint_data = Bits(OUTPUT, 64)
val exc = Bits(OUTPUT, 5)
} }
def apply[T <: Bits](data: T, en: Bool, resetVal: Bool) = {
val unrec_s = hardfloat.recodedFloatNToFloatN(io.in1, 23, 9) val r = Reg(resetVal = resetVal) { data.clone }
val unrec_d = hardfloat.recodedFloatNToFloatN(io.in1, 52, 12) when (en) { r := data }
r
io.store_data := Mux(io.single, Cat(unrec_s, unrec_s), unrec_d)
val scmp = new hardfloat.recodedFloatNCompare(23, 9)
scmp.io.a := io.in1
scmp.io.b := io.in2
val scmp_out = (io.cmd & Cat(scmp.io.a_lt_b, scmp.io.a_eq_b)).orR
val scmp_exc = (io.cmd & Cat(scmp.io.a_lt_b_invalid, scmp.io.a_eq_b_invalid)).orR << UFix(4)
val dcmp = new hardfloat.recodedFloatNCompare(52, 12)
dcmp.io.a := io.in1
dcmp.io.b := io.in2
val dcmp_out = (io.cmd & Cat(dcmp.io.a_lt_b, dcmp.io.a_eq_b)).orR
val dcmp_exc = (io.cmd & Cat(dcmp.io.a_lt_b_invalid, dcmp.io.a_eq_b_invalid)).orR << UFix(4)
val s2i = hardfloat.recodedFloatNToAny(io.in1, io.rm, ~io.cmd(1,0), 23, 9, 64)
val d2i = hardfloat.recodedFloatNToAny(io.in1, io.rm, ~io.cmd(1,0), 52, 12, 64)
// output muxing
val (out_s, exc_s) = (Bits(), Bits())
out_s := Cat(Fill(32, unrec_s(31)), unrec_s)
exc_s := Bits(0)
val (out_d, exc_d) = (Bits(), Bits())
out_d := unrec_d
exc_d := Bits(0)
when (io.cmd === FCMD_MTFSR || io.cmd === FCMD_MFFSR) {
out_s := io.fsr
} }
when (io.cmd === FCMD_CVT_W_FMT || io.cmd === FCMD_CVT_WU_FMT) {
out_s := Cat(Fill(32, s2i._1(31)), s2i._1(31,0))
exc_s := s2i._2
out_d := Cat(Fill(32, d2i._1(31)), d2i._1(31,0))
exc_d := d2i._2
}
when (io.cmd === FCMD_CVT_L_FMT || io.cmd === FCMD_CVT_LU_FMT) {
out_s := s2i._1
exc_s := s2i._2
out_d := d2i._1
exc_d := d2i._2
}
when (io.cmd === FCMD_EQ || io.cmd === FCMD_LT || io.cmd === FCMD_LE) {
out_s := scmp_out
exc_s := scmp_exc
out_d := dcmp_out
exc_d := dcmp_exc
}
io.toint_data := Mux(io.single, out_s, out_d)
io.exc := Mux(io.single, exc_s, exc_d)
io.lt_s := scmp.io.a_lt_b
io.lt_d := dcmp.io.a_lt_b
} }
class rocketFPUFastPipe extends Component class FPToInt extends Component
{ {
class Input extends Bundle {
val single = Bool()
val cmd = Bits(width = FCMD_WIDTH)
val rm = Bits(width = 3)
val fsr = Bits(width = FSR_WIDTH)
val in1 = Bits(width = 65)
val in2 = Bits(width = 65)
override def clone = new Input().asInstanceOf[this.type]
}
val io = new Bundle { val io = new Bundle {
val single = Bool(INPUT) val in = new PipeIO()(new Input).flip
val cmd = Bits(INPUT, FCMD_WIDTH) val out = new PipeIO()(new Bundle {
val rm = Bits(INPUT, 3) val lt = Bool()
val fromint = Bits(INPUT, 64) val store = Bits(width = 64)
val in1 = Bits(INPUT, 65) val toint = Bits(width = 64)
val in2 = Bits(INPUT, 65) val exc = Bits(width = 5)
val lt_s = Bool(INPUT) })
val lt_d = Bool(INPUT)
val out_s = Bits(OUTPUT, 33)
val exc_s = Bits(OUTPUT, 5)
val out_d = Bits(OUTPUT, 65)
val exc_d = Bits(OUTPUT, 5)
} }
val i2s = hardfloat.anyToRecodedFloatN(io.fromint, io.rm, ~io.cmd(1,0), 23, 9, 64) val in = Reg() { new Input }
val i2d = hardfloat.anyToRecodedFloatN(io.fromint, io.rm, ~io.cmd(1,0), 52, 12, 64) val valid = Reg(io.in.valid)
when (io.in.valid) {
def upconvert(x: Bits) = hardfloat.recodedFloatNToRecodedFloatM(x, Bits(0), 23, 9, 52, 12)._1
when (io.in.bits.cmd === FCMD_STORE) {
in.in1 := io.in.bits.in2
}.otherwise {
val doUpconvert = io.in.bits.single && io.in.bits.cmd != FCMD_MFTX
in.in1 := Mux(doUpconvert, upconvert(io.in.bits.in1), io.in.bits.in1)
in.in2 := Mux(doUpconvert, upconvert(io.in.bits.in2), io.in.bits.in2)
}
in.single := io.in.bits.single
in.cmd := io.in.bits.cmd
in.rm := io.in.bits.rm
in.fsr := io.in.bits.fsr
}
val unrec_s = hardfloat.recodedFloatNToFloatN(in.in1, 23, 9)
val unrec_d = hardfloat.recodedFloatNToFloatN(in.in1, 52, 12)
val dcmp = new hardfloat.recodedFloatNCompare(52, 12)
dcmp.io.a := in.in1
dcmp.io.b := in.in2
val dcmp_out = (in.cmd & Cat(dcmp.io.a_lt_b, dcmp.io.a_eq_b)).orR
val dcmp_exc = (in.cmd & Cat(dcmp.io.a_lt_b_invalid, dcmp.io.a_eq_b_invalid)).orR << UFix(4)
val d2i = hardfloat.recodedFloatNToAny(in.in1, in.rm, ~in.cmd(1,0), 52, 12, 64)
io.out.bits.toint := Mux(in.single, Cat(Fill(32, unrec_s(31)), unrec_s), unrec_d)
io.out.bits.exc := Bits(0)
when (in.cmd === FCMD_MTFSR || in.cmd === FCMD_MFFSR) {
io.out.bits.toint := io.in.bits.fsr
}
when (in.cmd === FCMD_CVT_W_FMT || in.cmd === FCMD_CVT_WU_FMT) {
io.out.bits.toint := Cat(Fill(32, d2i._1(31)), d2i._1(31,0))
io.out.bits.exc := d2i._2
}
when (in.cmd === FCMD_CVT_L_FMT || in.cmd === FCMD_CVT_LU_FMT) {
io.out.bits.toint := d2i._1
io.out.bits.exc := d2i._2
}
when (in.cmd === FCMD_EQ || in.cmd === FCMD_LT || in.cmd === FCMD_LE) {
io.out.bits.toint := dcmp_out
io.out.bits.exc := dcmp_exc
}
io.out.valid := valid
io.out.bits.store := Mux(in.single, Cat(unrec_s, unrec_s), unrec_d)
io.out.bits.lt := dcmp.io.a_lt_b
}
class FPResult extends Bundle
{
val data = Bits(width = 65)
val exc = Bits(width = 5)
}
class IntToFP(val latency: Int) extends Component
{
class Input extends Bundle {
val single = Bool()
val cmd = Bits(width = FCMD_WIDTH)
val rm = Bits(width = 3)
val data = Bits(width = 64)
override def clone = new Input().asInstanceOf[this.type]
}
val io = new Bundle {
val in = new PipeIO()(new Input).flip
val out = new PipeIO()(new FPResult)
}
val in = Pipe(io.in)
val mux = new FPResult
mux.exc := Bits(0)
mux.data := hardfloat.floatNToRecodedFloatN(in.bits.data, 52, 12)
when (in.bits.single) {
mux.data := hardfloat.floatNToRecodedFloatN(in.bits.data, 23, 9)
}
when (in.bits.cmd === FCMD_CVT_FMT_W || in.bits.cmd === FCMD_CVT_FMT_WU ||
in.bits.cmd === FCMD_CVT_FMT_L || in.bits.cmd === FCMD_CVT_FMT_LU) {
when (in.bits.single) {
val u = hardfloat.anyToRecodedFloatN(in.bits.data, in.bits.rm, ~in.bits.cmd(1,0), 23, 9, 64)
mux.data := Cat(Fix(-1, 32), u._1)
mux.exc := u._2
}.otherwise {
val u = hardfloat.anyToRecodedFloatN(in.bits.data, in.bits.rm, ~in.bits.cmd(1,0), 52, 12, 64)
mux.data := u._1
mux.exc := u._2
}
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class FPToFP(val latency: Int) extends Component
{
class Input extends Bundle {
val single = Bool()
val cmd = Bits(width = FCMD_WIDTH)
val rm = Bits(width = 3)
val in1 = Bits(width = 65)
val in2 = Bits(width = 65)
override def clone = new Input().asInstanceOf[this.type]
}
val io = new Bundle {
val in = new PipeIO()(new Input).flip
val out = new PipeIO()(new FPResult)
val lt = Bool(INPUT) // from FPToInt
}
val in = Pipe(io.in)
// fp->fp units // fp->fp units
val sign_s = Mux(io.cmd === FCMD_SGNJ, io.in2(32), val sign_s = Mux(in.bits.cmd === FCMD_SGNJ, in.bits.in2(32),
Mux(io.cmd === FCMD_SGNJN, ~io.in2(32), Mux(in.bits.cmd === FCMD_SGNJN, ~in.bits.in2(32),
io.in1(32) ^ io.in2(32))) // FCMD_SGNJX in.bits.in1(32) ^ in.bits.in2(32))) // FCMD_SGNJX
val sign_d = Mux(io.cmd === FCMD_SGNJ, io.in2(64), val sign_d = Mux(in.bits.cmd === FCMD_SGNJ, in.bits.in2(64),
Mux(io.cmd === FCMD_SGNJN, ~io.in2(64), Mux(in.bits.cmd === FCMD_SGNJN, ~in.bits.in2(64),
io.in1(64) ^ io.in2(64))) // FCMD_SGNJX in.bits.in1(64) ^ in.bits.in2(64))) // FCMD_SGNJX
val fsgnj = Cat(Mux(io.single, io.in1(64), sign_d), io.in1(63,33), val fsgnj = Cat(Mux(in.bits.single, in.bits.in1(64), sign_d), in.bits.in1(63,33),
Mux(io.single, sign_s, io.in1(32)), io.in1(31,0)) Mux(in.bits.single, sign_s, in.bits.in1(32)), in.bits.in1(31,0))
val s2d = hardfloat.recodedFloatNToRecodedFloatM(io.in1, io.rm, 23, 9, 52, 12) val s2d = hardfloat.recodedFloatNToRecodedFloatM(in.bits.in1, in.bits.rm, 23, 9, 52, 12)
val d2s = hardfloat.recodedFloatNToRecodedFloatM(io.in1, io.rm, 52, 12, 23, 9) val d2s = hardfloat.recodedFloatNToRecodedFloatM(in.bits.in1, in.bits.rm, 52, 12, 23, 9)
val isnan1 = Mux(io.single, io.in1(31,29) === Bits("b111"), io.in1(63,61) === Bits("b111")) val isnan1 = Mux(in.bits.single, in.bits.in1(31,29) === Bits("b111"), in.bits.in1(63,61) === Bits("b111"))
val isnan2 = Mux(io.single, io.in2(31,29) === Bits("b111"), io.in2(63,61) === Bits("b111")) val isnan2 = Mux(in.bits.single, in.bits.in2(31,29) === Bits("b111"), in.bits.in2(63,61) === Bits("b111"))
val issnan1 = isnan1 && ~Mux(io.single, io.in1(22), io.in1(51)) val issnan1 = isnan1 && ~Mux(in.bits.single, in.bits.in1(22), in.bits.in1(51))
val issnan2 = isnan2 && ~Mux(io.single, io.in2(22), io.in2(51)) val issnan2 = isnan2 && ~Mux(in.bits.single, in.bits.in2(22), in.bits.in2(51))
val minmax_exc = Cat(issnan1 || issnan2, Bits(0,4)) val minmax_exc = Cat(issnan1 || issnan2, Bits(0,4))
val min = io.cmd === FCMD_MIN val min = in.bits.cmd === FCMD_MIN
val lt = Mux(io.single, io.lt_s, io.lt_d) val minmax = Mux(isnan2 || !isnan1 && (min === io.lt), in.bits.in1, in.bits.in2)
val minmax = Mux(isnan2 || !isnan1 && (min === lt), io.in1, io.in2)
// output muxing val mux = new FPResult
val (out_s, exc_s) = (Bits(), Bits()) mux.data := fsgnj
out_s := Reg(hardfloat.floatNToRecodedFloatN(io.fromint, 23, 9)) mux.exc := Bits(0)
exc_s := Bits(0)
val (out_d, exc_d) = (Bits(), Bits())
out_d := Reg(hardfloat.floatNToRecodedFloatN(io.fromint, 52, 12))
exc_d := Bits(0)
val r_cmd = Reg(io.cmd) when (in.bits.cmd === FCMD_MIN || in.bits.cmd === FCMD_MAX) {
mux.data := minmax
when (r_cmd === FCMD_MTFSR || r_cmd === FCMD_MFFSR) {
out_s := Reg(io.fromint(FSR_WIDTH-1,0))
} }
when (r_cmd === FCMD_SGNJ || r_cmd === FCMD_SGNJN || r_cmd === FCMD_SGNJX) { when (in.bits.cmd === FCMD_CVT_FMT_S || in.bits.cmd === FCMD_CVT_FMT_D) {
val r_fsgnj = Reg(fsgnj) when (in.bits.single) {
out_s := r_fsgnj(32,0) mux.data := Cat(Fix(-1, 32), d2s._1)
out_d := r_fsgnj mux.exc := d2s._2
} }.otherwise {
when (r_cmd === FCMD_MIN || r_cmd === FCMD_MAX) { mux.data := s2d._1
val r_minmax = Reg(minmax) mux.exc := s2d._2
val r_minmax_exc = Reg(minmax_exc) }
out_s := r_minmax(32,0)
out_d := r_minmax
exc_s := r_minmax_exc
exc_d := r_minmax_exc
}
when (r_cmd === FCMD_CVT_FMT_S || r_cmd === FCMD_CVT_FMT_D) {
out_s := Reg(d2s._1)
exc_s := Reg(d2s._2)
out_d := Reg(s2d._1)
exc_d := Reg(s2d._2)
}
when (r_cmd === FCMD_CVT_FMT_W || r_cmd === FCMD_CVT_FMT_WU ||
r_cmd === FCMD_CVT_FMT_L || r_cmd === FCMD_CVT_FMT_LU) {
out_s := Reg(i2s._1)
exc_s := Reg(i2s._2)
out_d := Reg(i2d._1)
exc_d := Reg(i2d._2)
} }
io.out_s := out_s io.out <> Pipe(in.valid, mux, latency-1)
io.exc_s := exc_s
io.out_d := out_d
io.exc_d := exc_d
} }
class ioFMA(width: Int) extends Bundle { class ioFMA(width: Int) extends Bundle {
@ -348,7 +378,7 @@ class ioFMA(width: Int) extends Bundle {
val exc = Bits(OUTPUT, 5) val exc = Bits(OUTPUT, 5)
} }
class rocketFPUSFMAPipe(latency: Int) extends Component class rocketFPUSFMAPipe(val latency: Int) extends Component
{ {
val io = new ioFMA(33) val io = new ioFMA(33)
@ -365,6 +395,7 @@ class rocketFPUSFMAPipe(latency: Int) extends Component
val one = Bits("h80000000") val one = Bits("h80000000")
val zero = Cat(io.in1(32) ^ io.in2(32), Bits(0, 32)) val zero = Cat(io.in1(32) ^ io.in2(32), Bits(0, 32))
val valid = Reg(io.valid)
when (io.valid) { when (io.valid) {
cmd := Cat(io.cmd(1) & (cmd_fma || cmd_addsub), io.cmd(0)) cmd := Cat(io.cmd(1) & (cmd_fma || cmd_addsub), io.cmd(0))
rm := io.rm rm := io.rm
@ -380,11 +411,11 @@ class rocketFPUSFMAPipe(latency: Int) extends Component
fma.io.b := in2 fma.io.b := in2
fma.io.c := in3 fma.io.c := in3
io.out := ShiftRegister(latency-1, fma.io.out) io.out := Pipe(valid, fma.io.out, latency-1).bits
io.exc := ShiftRegister(latency-1, fma.io.exceptionFlags) io.exc := Pipe(valid, fma.io.exceptionFlags, latency-1).bits
} }
class rocketFPUDFMAPipe(latency: Int) extends Component class rocketFPUDFMAPipe(val latency: Int) extends Component
{ {
val io = new ioFMA(65) val io = new ioFMA(65)
@ -401,6 +432,7 @@ class rocketFPUDFMAPipe(latency: Int) extends Component
val one = Bits("h8000000000000000") val one = Bits("h8000000000000000")
val zero = Cat(io.in1(64) ^ io.in2(64), Bits(0, 64)) val zero = Cat(io.in1(64) ^ io.in2(64), Bits(0, 64))
val valid = Reg(io.valid)
when (io.valid) { when (io.valid) {
cmd := Cat(io.cmd(1) & (cmd_fma || cmd_addsub), io.cmd(0)) cmd := Cat(io.cmd(1) & (cmd_fma || cmd_addsub), io.cmd(0))
rm := io.rm rm := io.rm
@ -416,8 +448,8 @@ class rocketFPUDFMAPipe(latency: Int) extends Component
fma.io.b := in2 fma.io.b := in2
fma.io.c := in3 fma.io.c := in3
io.out := ShiftRegister(latency-1, fma.io.out) io.out := Pipe(valid, fma.io.out, latency-1).bits
io.exc := ShiftRegister(latency-1, fma.io.exceptionFlags) io.exc := Pipe(valid, fma.io.exceptionFlags, latency-1).bits
} }
class rocketFPU(sfma_latency: Int, dfma_latency: Int) extends Component class rocketFPU(sfma_latency: Int, dfma_latency: Int) extends Component
@ -434,16 +466,16 @@ class rocketFPU(sfma_latency: Int, dfma_latency: Int) extends Component
ex_reg_inst := io.dpath.inst ex_reg_inst := io.dpath.inst
} }
val ex_reg_valid = Reg(io.ctrl.valid, Bool(false)) val ex_reg_valid = Reg(io.ctrl.valid, Bool(false))
val mem_reg_valid = Reg(ex_reg_valid && !io.ctrl.killx, resetVal = Bool(false))
val killm = io.ctrl.killm || io.ctrl.nack_mem
val wb_reg_valid = Reg(mem_reg_valid && !killm, resetVal = Bool(false))
val fp_decoder = new rocketFPUDecoder val fp_decoder = new rocketFPUDecoder
fp_decoder.io.inst := io.dpath.inst fp_decoder.io.inst := io.dpath.inst
val ctrl = Reg() { new rocketFPUCtrlSigs } val ctrl = RegEn(fp_decoder.io.sigs, io.ctrl.valid)
when (io.ctrl.valid) { val mem_ctrl = RegEn(ctrl, ex_reg_valid)
ctrl := fp_decoder.io.sigs val wb_ctrl = RegEn(mem_ctrl, mem_reg_valid)
}
val mem_ctrl = Reg(ctrl)
val wb_ctrl = Reg(mem_ctrl)
// load response // load response
val load_wb = Reg(io.dpath.dmem_resp_val, resetVal = Bool(false)) val load_wb = Reg(io.dpath.dmem_resp_val, resetVal = Bool(false))
@ -457,8 +489,7 @@ class rocketFPU(sfma_latency: Int, dfma_latency: Int) extends Component
} }
val rec_s = hardfloat.floatNToRecodedFloatN(load_wb_data, 23, 9) val rec_s = hardfloat.floatNToRecodedFloatN(load_wb_data, 23, 9)
val rec_d = hardfloat.floatNToRecodedFloatN(load_wb_data, 52, 12) val rec_d = hardfloat.floatNToRecodedFloatN(load_wb_data, 52, 12)
val sp_msbs = Fix(-1, 32) val load_wb_data_recoded = Mux(load_wb_single, Cat(Fix(-1, 32), rec_s), rec_d)
val load_wb_data_recoded = Mux(load_wb_single, Cat(sp_msbs, rec_s), rec_d)
val fsr_rm = Reg() { Bits(width = 3) } val fsr_rm = Reg() { Bits(width = 3) }
val fsr_exc = Reg() { Bits(width = 5) } val fsr_exc = Reg() { Bits(width = 5) }
@ -472,143 +503,121 @@ class rocketFPU(sfma_latency: Int, dfma_latency: Int) extends Component
val ex_rs3 = regfile(ex_reg_inst(16,12)) val ex_rs3 = regfile(ex_reg_inst(16,12))
val ex_rm = Mux(ex_reg_inst(11,9) === Bits(7), fsr_rm, ex_reg_inst(11,9)) val ex_rm = Mux(ex_reg_inst(11,9) === Bits(7), fsr_rm, ex_reg_inst(11,9))
val mem_reg_valid = Reg(ex_reg_valid && !io.ctrl.killx, resetVal = Bool(false)) val fpiu = new FPToInt
val mem_fromint_data = Reg() { Bits() } fpiu.io.in.valid := ex_reg_valid && ctrl.toint
val mem_rs1 = Reg() { Bits() } fpiu.io.in.bits := ctrl
val mem_rs2 = Reg() { Bits() } fpiu.io.in.bits.rm := ex_rm
val mem_rs3 = Reg() { Bits() } fpiu.io.in.bits.fsr := Cat(fsr_rm, fsr_exc)
val mem_rm = Reg() { Bits() } fpiu.io.in.bits.in1 := ex_rs1
fpiu.io.in.bits.in2 := ex_rs2
when (ex_reg_valid) { io.dpath.store_data := fpiu.io.out.bits.store
mem_rm := ex_rm io.dpath.toint_data := fpiu.io.out.bits.toint
when (ctrl.fromint || ctrl.wrfsr) {
mem_fromint_data := io.dpath.fromint_data
}
when (ctrl.ren1) {
mem_rs1 := ex_rs1
}
when (ctrl.store) {
mem_rs1 := ex_rs2
}
when (ctrl.ren2) {
mem_rs2 := ex_rs2
}
when (ctrl.ren3) {
mem_rs3 := ex_rs3
}
}
// currently we assume FP stores and FP->int ops take 1 cycle (MEM) val ifpu = new IntToFP(3)
val fpiu = new rocketFPIntUnit ifpu.io.in.valid := ex_reg_valid && ctrl.fromint
fpiu.io.single := mem_ctrl.single ifpu.io.in.bits := ctrl
fpiu.io.cmd := mem_ctrl.cmd ifpu.io.in.bits.rm := ex_rm
fpiu.io.rm := mem_rm ifpu.io.in.bits.data := io.dpath.fromint_data
fpiu.io.fsr := Cat(fsr_rm, fsr_exc) val fpmu = new FPToFP(2)
fpiu.io.in1 := mem_rs1 fpmu.io.in.valid := ex_reg_valid && ctrl.fastpipe
fpiu.io.in2 := mem_rs2 fpmu.io.in.bits := ctrl
fpmu.io.in.bits.rm := ex_rm
io.dpath.store_data := fpiu.io.store_data fpmu.io.in.bits.in1 := ex_rs1
io.dpath.toint_data := fpiu.io.toint_data fpmu.io.in.bits.in2 := ex_rs2
fpmu.io.lt := fpiu.io.out.bits.lt
// 2-cycle pipe for int->FP and non-FMA FP->FP ops
val fastpipe = new rocketFPUFastPipe
fastpipe.io.single := mem_ctrl.single
fastpipe.io.cmd := mem_ctrl.cmd
fastpipe.io.rm := mem_rm
fastpipe.io.fromint := mem_fromint_data
fastpipe.io.in1 := mem_rs1
fastpipe.io.in2 := mem_rs2
fastpipe.io.lt_s := fpiu.io.lt_s
fastpipe.io.lt_d := fpiu.io.lt_d
val cmd_fma = mem_ctrl.cmd === FCMD_MADD || mem_ctrl.cmd === FCMD_MSUB || val cmd_fma = mem_ctrl.cmd === FCMD_MADD || mem_ctrl.cmd === FCMD_MSUB ||
mem_ctrl.cmd === FCMD_NMADD || mem_ctrl.cmd === FCMD_NMSUB mem_ctrl.cmd === FCMD_NMADD || mem_ctrl.cmd === FCMD_NMSUB
val cmd_addsub = mem_ctrl.cmd === FCMD_ADD || mem_ctrl.cmd === FCMD_SUB val cmd_addsub = mem_ctrl.cmd === FCMD_ADD || mem_ctrl.cmd === FCMD_SUB
val sfma = new rocketFPUSFMAPipe(sfma_latency-1) val sfma = new rocketFPUSFMAPipe(sfma_latency)
sfma.io.valid := io.sfma.valid || mem_reg_valid && mem_ctrl.fma && mem_ctrl.single sfma.io.valid := io.sfma.valid || ex_reg_valid && ctrl.fma && ctrl.single
sfma.io.in1 := Mux(io.sfma.valid, io.sfma.in1, mem_rs1) sfma.io.in1 := Mux(io.sfma.valid, io.sfma.in1, ex_rs1)
sfma.io.in2 := Mux(io.sfma.valid, io.sfma.in2, mem_rs2) sfma.io.in2 := Mux(io.sfma.valid, io.sfma.in2, ex_rs2)
sfma.io.in3 := Mux(io.sfma.valid, io.sfma.in3, mem_rs3) sfma.io.in3 := Mux(io.sfma.valid, io.sfma.in3, ex_rs3)
sfma.io.cmd := Mux(io.sfma.valid, io.sfma.cmd, mem_ctrl.cmd) sfma.io.cmd := Mux(io.sfma.valid, io.sfma.cmd, ctrl.cmd)
sfma.io.rm := Mux(io.sfma.valid, io.sfma.rm, mem_rm) sfma.io.rm := Mux(io.sfma.valid, io.sfma.rm, ex_rm)
io.sfma.out := sfma.io.out io.sfma.out := sfma.io.out
io.sfma.exc := sfma.io.exc io.sfma.exc := sfma.io.exc
val dfma = new rocketFPUDFMAPipe(dfma_latency-1) val dfma = new rocketFPUDFMAPipe(dfma_latency)
dfma.io.valid := io.dfma.valid || mem_reg_valid && mem_ctrl.fma && !mem_ctrl.single dfma.io.valid := io.dfma.valid || ex_reg_valid && ctrl.fma && !ctrl.single
dfma.io.in1 := Mux(io.dfma.valid, io.dfma.in1, mem_rs1) dfma.io.in1 := Mux(io.dfma.valid, io.dfma.in1, ex_rs1)
dfma.io.in2 := Mux(io.dfma.valid, io.dfma.in2, mem_rs2) dfma.io.in2 := Mux(io.dfma.valid, io.dfma.in2, ex_rs2)
dfma.io.in3 := Mux(io.dfma.valid, io.dfma.in3, mem_rs3) dfma.io.in3 := Mux(io.dfma.valid, io.dfma.in3, ex_rs3)
dfma.io.cmd := Mux(io.dfma.valid, io.dfma.cmd, mem_ctrl.cmd) dfma.io.cmd := Mux(io.dfma.valid, io.dfma.cmd, ctrl.cmd)
dfma.io.rm := Mux(io.dfma.valid, io.dfma.rm, mem_rm) dfma.io.rm := Mux(io.dfma.valid, io.dfma.rm, ex_rm)
io.dfma.out := dfma.io.out io.dfma.out := dfma.io.out
io.dfma.exc := dfma.io.exc io.dfma.exc := dfma.io.exc
val wb_reg_valid = Reg(mem_reg_valid && !io.ctrl.killm, resetVal = Bool(false))
val wb_toint_exc = Reg(fpiu.io.exc)
// writeback arbitration // writeback arbitration
val wen = Reg(resetVal = Bits(0, dfma_latency)) case class Pipe(p: Component, lat: Int, cond: (FPUCtrlSigs) => Bool, wdata: Bits, wexc: Bits)
val winfo = Vec(dfma_latency-1) { Reg() { Bits() } } val pipes = List(
val mem_wen = Reg(resetVal = Bool(false)) Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits.data, fpmu.io.out.bits.exc),
Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits.data, ifpu.io.out.bits.exc),
val fastpipe_latency = 2 Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.single, sfma.io.out, sfma.io.exc),
require(fastpipe_latency < sfma_latency && sfma_latency <= dfma_latency) Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && !c.single, dfma.io.out, dfma.io.exc))
val ex_stage_fu_latency = Mux(ctrl.fastpipe, UFix(fastpipe_latency-1), def latencyMask(c: FPUCtrlSigs, offset: Int) = {
Mux(ctrl.single, UFix(sfma_latency-1), require(pipes.forall(_.lat >= offset))
UFix(dfma_latency-1))) pipes.map(p => Mux(p.cond(c), UFix(1 << p.lat-offset), UFix(0))).reduce(_|_)
val mem_fu_latency = Reg(ex_stage_fu_latency - UFix(1))
val write_port_busy = Reg(ctrl.fastpipe && wen(fastpipe_latency) ||
Bool(sfma_latency < dfma_latency) && ctrl.fma && ctrl.single && wen(sfma_latency) ||
mem_wen && mem_fu_latency === ex_stage_fu_latency)
mem_wen := ex_reg_valid && !io.ctrl.killx && (ctrl.fma || ctrl.fastpipe)
val ex_stage_wsrc = Cat(ctrl.fastpipe, ctrl.single)
val mem_winfo = Reg(Cat(ex_reg_inst(31,27), ex_stage_wsrc))
for (i <- 0 until dfma_latency-2) {
winfo(i) := winfo(i+1)
} }
wen := wen >> UFix(1) def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), UFix(p._2), UFix(0))).reduce(_|_)
val maxLatency = pipes.map(_.lat).max
val memLatencyMask = latencyMask(mem_ctrl, 2)
val wen = Reg(resetVal = Bits(0, maxLatency-1))
val winfo = Vec(maxLatency-1) { Reg() { Bits() } }
val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
val (write_port_busy, mem_winfo) = (Reg{Bool()}, Reg{Bits()})
when (ex_reg_valid) {
write_port_busy := mem_wen && (memLatencyMask & latencyMask(ctrl, 1)).orR || (wen & latencyMask(ctrl, 0)).orR
mem_winfo := Cat(pipeid(ctrl), ex_reg_inst(31,27))
}
for (i <- 0 until maxLatency-2) {
when (wen(i+1)) { winfo(i) := winfo(i+1) }
}
wen := wen >> 1
when (mem_wen) { when (mem_wen) {
when (!io.ctrl.killm) { when (!killm) {
wen := (wen >> UFix(1)) | (UFix(1) << mem_fu_latency) wen := wen >> 1 | memLatencyMask
} }
for (i <- 0 until dfma_latency-1) { for (i <- 0 until maxLatency-1) {
when (!write_port_busy && UFix(i) === mem_fu_latency) { when (!write_port_busy && memLatencyMask(i)) {
winfo(i) := mem_winfo winfo(i) := mem_winfo
} }
} }
} }
val wsrc = winfo(0)(1,0) val waddr = winfo(0)(4,0).toUFix
val wdata = Mux(wsrc === UFix(0), dfma.io.out, // DFMA val wsrc = winfo(0) >> waddr.getWidth
Mux(wsrc === UFix(1), Cat(sp_msbs, sfma.io.out), // SFMA val wdata = (Vec(pipes.map(_.wdata)){Bits()})(wsrc)
Mux(wsrc === UFix(2), fastpipe.io.out_d, val wexc = (Vec(pipes.map(_.wexc)){Bits()})(wsrc)
Cat(sp_msbs, fastpipe.io.out_s))))
val wexc = Mux(wsrc === UFix(0), dfma.io.exc, // DFMA
Mux(wsrc === UFix(1), sfma.io.exc, // SFMA
Mux(wsrc === UFix(2), fastpipe.io.exc_d,
fastpipe.io.exc_s)))
val waddr = winfo(0).toUFix >> UFix(2)
when (wen(0)) { regfile(waddr(4,0)) := wdata } when (wen(0)) { regfile(waddr(4,0)) := wdata }
val wb_toint_exc = RegEn(fpiu.io.out.bits.exc, mem_ctrl.toint)
when (wb_reg_valid && wb_ctrl.toint || wen(0)) { when (wb_reg_valid && wb_ctrl.toint || wen(0)) {
fsr_exc := fsr_exc | fsr_exc := fsr_exc |
Fill(fsr_exc.getWidth, wb_reg_valid && wb_ctrl.toint) & wb_toint_exc | Fill(fsr_exc.getWidth, wb_reg_valid && wb_ctrl.toint) & wb_toint_exc |
Fill(fsr_exc.getWidth, wen(0)) & wexc Fill(fsr_exc.getWidth, wen(0)) & wexc
} }
val mem_fsr_wdata = RegEn(io.dpath.fromint_data(FSR_WIDTH-1,0), ex_reg_valid && ctrl.wrfsr)
val wb_fsr_wdata = RegEn(mem_fsr_wdata, mem_reg_valid && mem_ctrl.wrfsr)
when (wb_reg_valid && wb_ctrl.wrfsr) { when (wb_reg_valid && wb_ctrl.wrfsr) {
fsr_exc := fastpipe.io.out_s(4,0) fsr_exc := wb_fsr_wdata
fsr_rm := fastpipe.io.out_s(7,5) fsr_rm := wb_fsr_wdata >> fsr_exc.getWidth
} }
val fp_inflight = wb_reg_valid && wb_ctrl.toint || wen.orR val fp_inflight = wb_reg_valid && wb_ctrl.toint || wen.orR
val fsr_busy = mem_ctrl.rdfsr && fp_inflight || wb_reg_valid && wb_ctrl.wrfsr val fsr_busy = mem_ctrl.rdfsr && fp_inflight || wb_reg_valid && wb_ctrl.wrfsr
val units_busy = mem_reg_valid && mem_ctrl.fma && (io.sfma.valid && mem_ctrl.single || io.dfma.valid && !mem_ctrl.single) val units_busy = mem_reg_valid && mem_ctrl.fma && Reg(Mux(ctrl.single, io.sfma.valid, io.dfma.valid))
io.ctrl.nack_mem := fsr_busy || units_busy || write_port_busy io.ctrl.nack_mem := fsr_busy || units_busy || write_port_busy
io.ctrl.dec <> fp_decoder.io.sigs io.ctrl.dec <> fp_decoder.io.sigs
def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(Bool(false))(_||_)
io.ctrl.sboard_set := wb_reg_valid && Reg(useScoreboard(_._1.cond(mem_ctrl)))
io.ctrl.sboard_clr := wen(0) && useScoreboard(x => wsrc === UFix(x._2))
io.ctrl.sboard_clra := waddr
// we don't currently support round-max-magnitude (rm=4) // we don't currently support round-max-magnitude (rm=4)
io.ctrl.illegal_rm := ex_rm(2) io.ctrl.illegal_rm := ex_rm(2)
io.ctrl.sboard_clr := wen(0) && !wsrc(1).toBool // only for FMA pipes
io.ctrl.sboard_clra := waddr
} }

6
rocket/src/main/scala/multiplier.scala
View File

@ -8,11 +8,11 @@ import hwacha.Constants._
class ioMultiplier extends Bundle { class ioMultiplier extends Bundle {
val req = new io_imul_req().flip val req = new io_imul_req().flip
val req_tag = Bits(INPUT, 5) val req_tag = UFix(INPUT, 5)
val req_kill = Bool(INPUT) val req_kill = Bool(INPUT)
val resp_val = Bool(OUTPUT) val resp_val = Bool(OUTPUT)
val resp_rdy = Bool(INPUT) val resp_rdy = Bool(INPUT)
val resp_tag = Bits(OUTPUT, 5) val resp_tag = UFix(OUTPUT, 5)
val resp_bits = Bits(OUTPUT, SZ_XLEN) val resp_bits = Bits(OUTPUT, SZ_XLEN)
} }
@ -71,7 +71,7 @@ class rocketMultiplier(unroll: Int = 1, earlyOut: Boolean = false) extends Compo
val r_val = Reg(resetVal = Bool(false)); val r_val = Reg(resetVal = Bool(false));
val r_dw = Reg { Bits() } val r_dw = Reg { Bits() }
val r_fn = Reg { Bits() } val r_fn = Reg { Bits() }
val r_tag = Reg { Bits() } val r_tag = Reg { UFix() }
val r_lhs = Reg { Bits() } val r_lhs = Reg { Bits() }
val r_prod= Reg { Bits(width = w*2) } val r_prod= Reg { Bits(width = w*2) }
val r_lsb = Reg { Bits() } val r_lsb = Reg { Bits() }

2
rocket/src/main/scala/tile.scala
View File

@ -13,7 +13,7 @@ class Tile(resetSignal: Bool = null)(implicit conf: RocketConfiguration) extends
} }
val cpu = new rocketProc val cpu = new rocketProc
val icache = new Frontend(ICacheConfig(128, 4)) // 128 sets x 4 ways (32KB) val icache = new Frontend(ICacheConfig(4, 1)) // 128 sets x 4 ways (32KB)
val dcache = new HellaCache val dcache = new HellaCache
val arbiter = new rocketMemArbiter(DMEM_PORTS) val arbiter = new rocketMemArbiter(DMEM_PORTS)