riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

aggressively clock gate int and fp datapaths

Browse Source
This commit is contained in:
Andrew Waterman
2012-11-04 16:40:14 -08:00
parent bd2d61de03
commit 7380c9fe60
8 changed files with 568 additions and 639 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
rocket/src/main/scala/tile.scala
View File

@ -13,7 +13,7 @@ class Tile(resetSignal: Bool = null)(implicit conf: RocketConfiguration) extends
}
val cpu = new rocketProc
val icache = new Frontend(ICacheConfig(128, 4)) // 128 sets x 4 ways (32KB)
val icache = new Frontend(ICacheConfig(4, 1)) // 128 sets x 4 ways (32KB)
val dcache = new HellaCache
val arbiter = new rocketMemArbiter(DMEM_PORTS)