riscv/rocket-chip
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print stack trace if elaboration fails

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This commit is contained in:
Andrew Waterman 2012-11-20 05:39:48 -08:00
parent 4d73e6e38a
commit 7330deb13a
2 changed files with 3 additions and 3 deletions
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2
Makefrag
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@ -4,7 +4,7 @@ MODEL := Top
CXX := g++
CXXFLAGS := -O2
SBT := java -Xmx1024M -Xss8M -XX:MaxPermSize=128M -jar sbt-launch.jar
SBT := java -Xmx2048M -Xss8M -XX:MaxPermSize=128M -jar sbt-launch.jar
#--------------------------------------------------------------------
# Tests

4
project/build.scala
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@ -12,7 +12,8 @@ object BuildSettings extends Build {
//unmanagedBase <<= baseDirectory { base => base / ".." / custom_lib" },
organization := buildOrganization,
version := buildVersion,
scalaVersion := buildScalaVersion
scalaVersion := buildScalaVersion,
traceLevel := 15
)
lazy val chisel = Project("chisel", file("chisel"), settings = buildSettings)
@ -61,5 +62,4 @@ object BuildSettings extends Build {
}
}
)
}