multibeat TL; passes all tests
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@ -158,50 +158,3 @@ object Random
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private def partition(value: UInt, slices: Int) =
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Vec.tabulate(slices)(i => value < round((i << value.getWidth).toDouble / slices))
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}
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class FlowThroughSerializer[T <: HasTileLinkData](gen: LogicalNetworkIO[T], n: Int, doSer: T => Bool) extends Module {
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val io = new Bundle {
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val in = Decoupled(gen.clone).flip
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val out = Decoupled(gen.clone)
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val cnt = UInt(OUTPUT, log2Up(n))
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val done = Bool(OUTPUT)
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}
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require(io.in.bits.payload.data.getWidth % n == 0)
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val narrowWidth = io.in.bits.payload.data.getWidth / n
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val cnt = Reg(init=UInt(0, width = log2Up(n)))
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val wrap = cnt === UInt(n-1)
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val rbits = Reg(init=io.in.bits)
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val active = Reg(init=Bool(false))
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val shifter = Vec.fill(n){Bits(width = narrowWidth)}
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(0 until n).foreach {
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i => shifter(i) := rbits.payload.data((i+1)*narrowWidth-1,i*narrowWidth)
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}
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io.done := Bool(false)
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io.cnt := cnt
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io.in.ready := !active
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io.out.valid := active || io.in.valid
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io.out.bits := io.in.bits
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when(!active && io.in.valid) {
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when(doSer(io.in.bits.payload)) {
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cnt := Mux(io.out.ready, UInt(1), UInt(0))
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rbits := io.in.bits
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active := Bool(true)
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}
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io.done := !doSer(io.in.bits.payload)
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}
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when(active) {
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io.out.bits := rbits
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io.out.bits.payload.data := shifter(cnt)
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when(io.out.ready) {
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cnt := cnt + UInt(1)
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when(wrap) {
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cnt := UInt(0)
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io.done := Bool(true)
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active := Bool(false)
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}
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}
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}
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}
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