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tilelink2: factor out the OH1ToOH function

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This commit is contained in:
Wesley W. Terpstra 2016-10-16 19:57:56 -07:00
parent d09f43c32f
commit 72e5a97d40
2 changed files with 4 additions and 3 deletions
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4
src/main/scala/uncore/axi4/Fragmenter.scala
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@ -7,7 +7,7 @@ import chisel3.internal.sourceinfo.SourceInfo
import chisel3.util.IrrevocableIO import chisel3.util.IrrevocableIO
import diplomacy._ import diplomacy._
import scala.math.{min,max} import scala.math.{min,max}
import uncore.tilelink2.{leftOR, rightOR, UIntToOH1} import uncore.tilelink2.{leftOR, rightOR, UIntToOH1, OH1ToOH}
// lite: masters all use only one ID => reads will not be interleaved // lite: masters all use only one ID => reads will not be interleaved
class AXI4Fragmenter(lite: Boolean = false, maxInFlight: Int = 32, combinational: Boolean = true) extends LazyModule class AXI4Fragmenter(lite: Boolean = false, maxInFlight: Int = 32, combinational: Boolean = true) extends LazyModule
@ -100,7 +100,7 @@ class AXI4Fragmenter(lite: Boolean = false, maxInFlight: Int = 32, combinational
// The number of beats-1 to execute // The number of beats-1 to execute
val beats1 = Mux(bad, UInt(0), maxSupported1) val beats1 = Mux(bad, UInt(0), maxSupported1)
val beats = ~(~(beats1 << 1 | UInt(1)) | beats1) // beats1 + 1 val beats = OH1ToOH(beats1) // beats1 + 1
val inc_addr = addr + (beats << a.bits.size) // address after adding transfer val inc_addr = addr + (beats << a.bits.size) // address after adding transfer
val wrapMask = a.bits.bytes1() // only these bits may change, if wrapping val wrapMask = a.bits.bytes1() // only these bits may change, if wrapping

3
src/main/scala/uncore/tilelink2/package.scala
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@ -8,7 +8,8 @@ package object tilelink2
type TLOutwardNode = OutwardNodeHandle[TLClientPortParameters, TLManagerPortParameters, TLBundle] type TLOutwardNode = OutwardNodeHandle[TLClientPortParameters, TLManagerPortParameters, TLBundle]
type TLAsyncOutwardNode = OutwardNodeHandle[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle] type TLAsyncOutwardNode = OutwardNodeHandle[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]
type IntOutwardNode = OutwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]] type IntOutwardNode = OutwardNodeHandle[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]
def OH1ToUInt(x: UInt) = OHToUInt((x << 1 | UInt(1)) ^ x) def OH1ToOH(x: UInt) = (x << 1 | UInt(1)) & ~Cat(UInt(0, width=1), x)
def OH1ToUInt(x: UInt) = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int) = ~(SInt(-1, width=width).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt, width: Int) = ~(SInt(-1, width=width).asUInt << x)(width-1, 0)
def trailingZeros(x: Int) = if (x > 0) Some(log2Ceil(x & -x)) else None def trailingZeros(x: Int) = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits // Fill 1s from low bits to high bits