riscv/rocket-chip
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update to new chisel

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This commit is contained in:
Andrew Waterman
2012-02-11 17:20:33 -08:00
parent f8b937d590
commit 725190d0ee
17 changed files with 626 additions and 656 deletions
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8
rocket/src/main/scala/fpu.scala
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@ -126,7 +126,7 @@ class rocketFPU extends Component
val ex_reg_inst = Reg() { Bits() }
when (io.req_valid) {
ex_reg_inst <== io.req_inst
ex_reg_inst := io.req_inst
}
// load response
@ -135,12 +135,12 @@ class rocketFPU extends Component
val load_wb_data = Reg() { Bits() }
val load_wb_tag = Reg() { UFix() }
when (dmem_resp_val_fpu) {
load_wb_data <== io.dmem.resp_data
load_wb_tag <== io.dmem.resp_tag.toUFix >> UFix(1)
load_wb_data := io.dmem.resp_data
load_wb_tag := io.dmem.resp_tag.toUFix >> UFix(1)
}
// regfile
val regfile = Mem4(32, load_wb_data);
val regfile = Mem(32, load_wb_data);
regfile.setReadLatency(0);
regfile.setTarget('inst);
regfile.write(load_wb_tag, load_wb_data, load_wb);