riscv/rocket-chip
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update to new chisel

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This commit is contained in:
Andrew Waterman
2012-02-11 17:20:33 -08:00
parent f8b937d590
commit 725190d0ee
17 changed files with 626 additions and 656 deletions
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188
rocket/src/main/scala/dpath_util.scala
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@ -40,13 +40,10 @@ class rocketDpathBTB(entries: Int) extends Component
val my_clr = io.clr && my_hit || io.invalidate
val my_wen = io.wen && (my_hit || !hit && UFix(i) === repl_way)
when (my_clr) {
valid <== Bool(false)
}
valid := !my_clr && (valid || my_wen)
when (my_wen) {
valid <== Bool(true)
tag <== io.correct_pc
target <== io.correct_target
tag := io.correct_pc
target := io.correct_target
}
hit_reduction = hit_reduction || my_hit
@ -66,14 +63,14 @@ class ioDpathPCR extends Bundle()
val r = new ioReadPort();
val w = new ioWritePort();
val status = Bits(17, OUTPUT);
val status = Bits(17, OUTPUT);
val ptbr = UFix(PADDR_BITS, OUTPUT);
val evec = UFix(VADDR_BITS, OUTPUT);
val exception = Bool(INPUT);
val cause = UFix(5, INPUT);
val cause = UFix(5, INPUT);
val badvaddr_wen = Bool(INPUT);
val pc = UFix(VADDR_BITS+1, INPUT);
val eret = Bool(INPUT);
val pc = UFix(VADDR_BITS+1, INPUT);
val eret = Bool(INPUT);
val ei = Bool(INPUT);
val di = Bool(INPUT);
val ptbr_wen = Bool(OUTPUT);
@ -120,12 +117,12 @@ class rocketDpathPCR extends Component
val reg_status = Cat(reg_status_sx, reg_status_ux, reg_status_s, reg_status_ps, reg_status_ec, reg_status_ev, reg_status_ef, reg_status_et);
val rdata = Wire() { Bits() };
io.ptbr_wen := reg_status_vm.toBool && !io.exception && io.w.en && (io.w.addr === PCR_PTBR);
io.status := Cat(reg_status_vm, reg_status_im, reg_status);
io.ptbr_wen := reg_status_vm.toBool && io.w.en && (io.w.addr === PCR_PTBR);
io.status := Cat(reg_status_vm, reg_status_im, reg_status);
io.evec := reg_ebase;
io.ptbr := reg_ptbr;
io.host.to := Mux(io.host.from_wen, Bits(0), reg_tohost);
io.debug.error_mode := reg_error_mode;
io.host.to := Mux(io.host.from_wen, Bits(0), reg_tohost);
io.debug.error_mode := reg_error_mode;
io.r.data := rdata;
io.vecbank := reg_vecbank
@ -139,100 +136,99 @@ class rocketDpathPCR extends Component
io.console_val := console_wen;
when (io.host.from_wen) {
reg_tohost <== Bits(0);
reg_fromhost <== io.host.from;
}
otherwise {
when (!io.exception && io.w.en && (io.w.addr === PCR_TOHOST)) {
reg_tohost <== io.w.data;
reg_fromhost <== Bits(0);
}
reg_tohost := Bits(0);
reg_fromhost := io.host.from;
}
.elsewhen (io.w.en && (io.w.addr === PCR_TOHOST)) {
reg_tohost := io.w.data;
reg_fromhost := Bits(0);
}
val badvaddr_sign = Mux(io.w.data(VADDR_BITS-1), ~io.w.data(63,VADDR_BITS) === UFix(0), io.w.data(63,VADDR_BITS) != UFix(0))
when (io.badvaddr_wen) {
reg_badvaddr <== Cat(badvaddr_sign, io.w.data(VADDR_BITS-1,0)).toUFix;
}
when (io.exception && !reg_status_et) {
reg_error_mode <== Bool(true);
}
when (io.exception && reg_status_et) {
reg_status_s <== Bool(true);
reg_status_ps <== reg_status_s;
reg_status_et <== Bool(false);
reg_epc <== io.pc;
reg_cause <== io.cause;
}
when (!io.exception && io.di) {
reg_status_et <== Bool(false);
}
when (!io.exception && io.ei) {
reg_status_et <== Bool(true);
}
when (!io.exception && io.eret) {
reg_status_s <== reg_status_ps;
reg_status_et <== Bool(true);
reg_badvaddr := Cat(badvaddr_sign, io.w.data(VADDR_BITS-1,0)).toUFix;
}
when (!io.exception && !io.eret && io.w.en) {
when (io.w.addr === PCR_STATUS) {
reg_status_vm <== io.w.data(SR_VM).toBool;
reg_status_im <== io.w.data(15,8);
reg_status_sx <== io.w.data(SR_SX).toBool;
reg_status_ux <== io.w.data(SR_UX).toBool;
reg_status_s <== io.w.data(SR_S).toBool;
reg_status_ps <== io.w.data(SR_PS).toBool;
reg_status_ev <== Bool(HAVE_VEC) && io.w.data(SR_EV).toBool;
reg_status_ef <== Bool(HAVE_FPU) && io.w.data(SR_EF).toBool;
reg_status_ec <== Bool(HAVE_RVC) && io.w.data(SR_EC).toBool;
reg_status_et <== io.w.data(SR_ET).toBool;
}
when (io.w.addr === PCR_EPC) { reg_epc <== io.w.data(VADDR_BITS,0).toUFix; }
when (io.w.addr === PCR_BADVADDR) { reg_badvaddr <== io.w.data(VADDR_BITS,0).toUFix; }
when (io.w.addr === PCR_EVEC) { reg_ebase <== io.w.data(VADDR_BITS-1,0).toUFix; }
when (io.w.addr === PCR_COUNT) { reg_count <== io.w.data(31,0).toUFix; }
when (io.w.addr === PCR_COMPARE) { reg_compare <== io.w.data(31,0).toUFix; r_irq_timer <== Bool(false); }
when (io.w.addr === PCR_CAUSE) { reg_cause <== io.w.data(4,0); }
when (io.w.addr === PCR_FROMHOST) { reg_fromhost <== io.w.data; }
when (io.w.addr === PCR_SEND_IPI) { r_irq_ipi <== Bool(true); }
when (io.w.addr === PCR_CLR_IPI) { r_irq_ipi <== Bool(false); }
when (io.w.addr === PCR_K0) { reg_k0 <== io.w.data; }
when (io.w.addr === PCR_K1) { reg_k1 <== io.w.data; }
when (io.w.addr === PCR_PTBR) { reg_ptbr <== Cat(io.w.data(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; }
when (io.w.addr === PCR_VECBANK) { reg_vecbank <== io.w.data(7,0) }
when (io.exception) {
when (!reg_status_et) {
reg_error_mode := Bool(true)
}
.otherwise {
reg_status_s := Bool(true);
reg_status_ps := reg_status_s;
reg_status_et := Bool(false);
reg_epc := io.pc;
reg_cause := io.cause;
}
}
otherwise {
reg_count <== reg_count + UFix(1);
when (io.di) {
reg_status_et := Bool(false);
}
when (io.ei) {
reg_status_et := Bool(true);
}
when (io.eret) {
reg_status_s := reg_status_ps;
reg_status_et := Bool(true);
}
when (reg_count === reg_compare) {
r_irq_timer <== Bool(true);
r_irq_timer := Bool(true);
}
reg_count := reg_count + UFix(1);
io.irq_timer := r_irq_timer;
io.irq_ipi := r_irq_ipi;
when (!io.r.en) { rdata <== Bits(0,64); }
switch (io.r.addr) {
is (PCR_STATUS) { rdata <== Cat(Bits(0,47), reg_status_vm, reg_status_im, reg_status); }
is (PCR_EPC) { rdata <== Cat(Fill(64-VADDR_BITS-1, reg_epc(VADDR_BITS)), reg_epc); }
is (PCR_BADVADDR) { rdata <== Cat(Fill(64-VADDR_BITS-1, reg_badvaddr(VADDR_BITS)), reg_badvaddr); }
is (PCR_EVEC) { rdata <== Cat(Fill(64-VADDR_BITS, reg_ebase(VADDR_BITS-1)), reg_ebase); }
is (PCR_COUNT) { rdata <== Cat(Fill(32, reg_count(31)), reg_count); }
is (PCR_COMPARE) { rdata <== Cat(Fill(32, reg_compare(31)), reg_compare); }
is (PCR_CAUSE) { rdata <== Cat(Bits(0,59), reg_cause); }
is (PCR_COREID) { rdata <== Bits(COREID,64); }
is (PCR_FROMHOST) { rdata <== reg_fromhost; }
is (PCR_TOHOST) { rdata <== reg_tohost; }
is (PCR_K0) { rdata <== reg_k0; }
is (PCR_K1) { rdata <== reg_k1; }
is (PCR_PTBR) { rdata <== Cat(Bits(0,64-PADDR_BITS), reg_ptbr); }
is (PCR_VECBANK) { rdata <== Cat(Bits(0, 56), reg_vecbank) }
otherwise { rdata <== Bits(0,64); }
when (io.w.en) {
when (io.w.addr === PCR_STATUS) {
reg_status_vm := io.w.data(SR_VM).toBool;
reg_status_im := io.w.data(15,8);
reg_status_sx := io.w.data(SR_SX).toBool;
reg_status_ux := io.w.data(SR_UX).toBool;
reg_status_s := io.w.data(SR_S).toBool;
reg_status_ps := io.w.data(SR_PS).toBool;
reg_status_ev := Bool(HAVE_VEC) && io.w.data(SR_EV).toBool;
reg_status_ef := Bool(HAVE_FPU) && io.w.data(SR_EF).toBool;
reg_status_ec := Bool(HAVE_RVC) && io.w.data(SR_EC).toBool;
reg_status_et := io.w.data(SR_ET).toBool;
}
when (io.w.addr === PCR_EPC) { reg_epc := io.w.data(VADDR_BITS,0).toUFix; }
when (io.w.addr === PCR_BADVADDR) { reg_badvaddr := io.w.data(VADDR_BITS,0).toUFix; }
when (io.w.addr === PCR_EVEC) { reg_ebase := io.w.data(VADDR_BITS-1,0).toUFix; }
when (io.w.addr === PCR_COUNT) { reg_count := io.w.data(31,0).toUFix; }
when (io.w.addr === PCR_COMPARE) { reg_compare := io.w.data(31,0).toUFix; r_irq_timer := Bool(false); }
when (io.w.addr === PCR_CAUSE) { reg_cause := io.w.data(4,0); }
when (io.w.addr === PCR_FROMHOST) { reg_fromhost := io.w.data; }
when (io.w.addr === PCR_SEND_IPI) { r_irq_ipi := Bool(true); }
when (io.w.addr === PCR_CLR_IPI) { r_irq_ipi := Bool(false); }
when (io.w.addr === PCR_K0) { reg_k0 := io.w.data; }
when (io.w.addr === PCR_K1) { reg_k1 := io.w.data; }
when (io.w.addr === PCR_PTBR) { reg_ptbr := Cat(io.w.data(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; }
when (io.w.addr === PCR_VECBANK) { reg_vecbank := io.w.data(7,0) }
}
rdata := Bits(0, 64)
when (io.r.en) {
switch (io.r.addr) {
is (PCR_STATUS) { rdata := Cat(Bits(0,47), reg_status_vm, reg_status_im, reg_status); }
is (PCR_EPC) { rdata := Cat(Fill(64-VADDR_BITS-1, reg_epc(VADDR_BITS)), reg_epc); }
is (PCR_BADVADDR) { rdata := Cat(Fill(64-VADDR_BITS-1, reg_badvaddr(VADDR_BITS)), reg_badvaddr); }
is (PCR_EVEC) { rdata := Cat(Fill(64-VADDR_BITS, reg_ebase(VADDR_BITS-1)), reg_ebase); }
is (PCR_COUNT) { rdata := Cat(Fill(32, reg_count(31)), reg_count); }
is (PCR_COMPARE) { rdata := Cat(Fill(32, reg_compare(31)), reg_compare); }
is (PCR_CAUSE) { rdata := Cat(Bits(0,59), reg_cause); }
is (PCR_COREID) { rdata := Bits(COREID,64); }
is (PCR_FROMHOST) { rdata := reg_fromhost; }
is (PCR_TOHOST) { rdata := reg_tohost; }
is (PCR_K0) { rdata := reg_k0; }
is (PCR_K1) { rdata := reg_k1; }
is (PCR_PTBR) { rdata := Cat(Bits(0,64-PADDR_BITS), reg_ptbr); }
is (PCR_VECBANK) { rdata := Cat(Bits(0, 56), reg_vecbank) }
}
}
}
@ -261,7 +257,7 @@ class rocketDpathRegfile extends Component
{
override val io = new ioRegfile();
val regfile = Mem4(32, io.w0.data);
val regfile = Mem(32, io.w0.data);
regfile.setReadLatency(0);
regfile.setTarget('inst);
regfile.write(io.w0.addr, io.w0.data, io.w0.en);