riscv/rocket-chip
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fix writeback bug

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This commit is contained in:
Andrew Waterman 2012-04-13 03:16:48 -07:00
parent 00d934cfac
commit 724735f13f
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/nbdcache.scala
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@ -235,7 +235,7 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component {
when (reply) { state := s_meta_clear } when (reply) { state := s_meta_clear }
when (abort) { state := s_wb_req } when (abort) { state := s_wb_req }
} }
when (state === s_wb_req && io.meta_req.ready) { when (state === s_wb_req) {
when (io.probe_writeback.valid && idx_match) { state := s_refill_req } when (io.probe_writeback.valid && idx_match) { state := s_refill_req }
.elsewhen (io.wb_req.ready) { state := s_wb_resp } .elsewhen (io.wb_req.ready) { state := s_wb_resp }
} }