Merge pull request #971 from freechipsproject/bump-chisel-firrtl
Bump chisel3 and firrtl, update plugin versions
This commit is contained in:
commit
723af5e6b6
2
chisel3
2
chisel3
@ -1 +1 @@
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Subproject commit bb12fe7f61d12f51cf5d56b2a66aca0a1234abb3
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Subproject commit e2c5c128f6509805f71aeca790809b3e9a8fe84d
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2
firrtl
2
firrtl
@ -1 +1 @@
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Subproject commit f8572ba6532359e8a0f1bc34f3eb8241a29129ab
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Subproject commit 5e23294dc6ac3c1937c9f071f970178c9f724037
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@ -1 +1 @@
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sbt.version=0.13.12
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sbt.version=0.13.16
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@ -11,7 +11,7 @@ object BuildSettings extends Build {
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override lazy val settings = super.settings ++ Seq(
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override lazy val settings = super.settings ++ Seq(
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organization := "berkeley",
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organization := "berkeley",
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version := "1.2",
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version := "1.2",
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scalaVersion := "2.11.7",
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scalaVersion := "2.11.11",
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parallelExecution in Global := false,
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parallelExecution in Global := false,
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traceLevel := 15,
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traceLevel := 15,
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scalacOptions ++= Seq("-deprecation","-unchecked"),
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scalacOptions ++= Seq("-deprecation","-unchecked"),
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@ -1,13 +1,13 @@
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resolvers += "jgit-repo" at "http://download.eclipse.org/jgit/maven"
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resolvers += "jgit-repo" at "http://download.eclipse.org/jgit/maven"
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addSbtPlugin("com.typesafe.sbt" % "sbt-ghpages" % "0.5.3")
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addSbtPlugin("com.typesafe.sbt" % "sbt-ghpages" % "0.6.2")
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addSbtPlugin("com.typesafe.sbt" % "sbt-site" % "0.8.1")
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addSbtPlugin("com.typesafe.sbt" % "sbt-site" % "1.3.0")
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addSbtPlugin("com.eed3si9n" % "sbt-buildinfo" % "0.7.0")
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addSbtPlugin("com.eed3si9n" % "sbt-buildinfo" % "0.7.0")
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addSbtPlugin("org.xerial.sbt" % "sbt-pack" % "0.8.0")
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addSbtPlugin("org.xerial.sbt" % "sbt-pack" % "0.8.0")
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addSbtPlugin("com.eed3si9n" % "sbt-unidoc" % "0.3.3")
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addSbtPlugin("com.eed3si9n" % "sbt-unidoc" % "0.4.1")
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addSbtPlugin("org.scoverage" % "sbt-scoverage" % "1.5.1")
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addSbtPlugin("org.scoverage" % "sbt-scoverage" % "1.5.1")
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@ -150,7 +150,7 @@ class CaptureUpdateChain[+T <: Data, +V <: Data](genCapture: T, genUpdate: V) ex
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io.chainOut.data := regs(0)
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io.chainOut.data := regs(0)
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val updateBits = Cat(regs.reverse)(updateWidth-1, 0)
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val updateBits = Cat(regs.reverse)(updateWidth-1, 0)
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io.update.bits := io.update.bits.fromBits(updateBits)
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io.update.bits := updateBits.asTypeOf(io.update.bits)
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val captureBits = io.capture.bits.asUInt()
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val captureBits = io.capture.bits.asUInt()
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