riscv/rocket-chip
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Mitigate some more PMP critical paths

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This commit is contained in:
Andrew Waterman
2017-03-15 18:00:32 -07:00
parent 7484f27ed3
commit 723352c3e2
5 changed files with 31 additions and 25 deletions
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12
src/main/scala/rocket/PTW.scala
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@ -79,6 +79,7 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
val count = Reg(UInt(width = log2Up(pgLevels)))
val s1_kill = Reg(next = Bool(false))
val resp_valid = Reg(next = Bool(false))
val exception = Reg(next = io.mem.xcpt.pf.ld)
val r_req = Reg(new PTWReq)
val r_req_dest = Reg(Bits())
@ -156,7 +157,6 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
is (s_req) {
when (pte_cache_hit) {
s1_kill := true
state := s_req
count := count + 1
r_pte.ppn := pte_cache_data
}.elsewhen (io.mem.req.ready) {
@ -165,11 +165,6 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
}
is (s_wait1) {
state := s_wait2
when (io.mem.xcpt.pf.ld) {
r_pte.v := false
state := s_ready
resp_valid := true
}
}
is (s_wait2) {
when (io.mem.s2_nack) {
@ -185,6 +180,11 @@ class PTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
resp_valid := true
}
}
when (exception) {
r_pte.v := false
state := s_ready
resp_valid := true
}
}
}
}