riscv/rocket-chip
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Don't special-case power-of-2 replacement policy for BTB

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PLRU wasn't implemented correctly for the BTB, since it wasn't
increasing the priority on replacement, only on usage.  Regardless,
this should be a second-order effect, so using FIFO always is fine.
This commit is contained in:
Andrew Waterman 2017-01-05 18:08:12 -08:00 committed by Henry Cook
parent c531093898
commit 71c4b000b3
1 changed files with 1 additions and 9 deletions
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10
src/main/scala/rocket/btb.scala
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@ -182,15 +182,7 @@ class BTB(implicit p: Parameters) extends BtbModule {
val updateHit = if (updatesOutOfOrder) updateHits.orR else r_btb_update.bits.prediction.valid val updateHit = if (updatesOutOfOrder) updateHits.orR else r_btb_update.bits.prediction.valid
val updateHitAddr = if (updatesOutOfOrder) OHToUInt(updateHits) else r_btb_update.bits.prediction.bits.entry val updateHitAddr = if (updatesOutOfOrder) OHToUInt(updateHits) else r_btb_update.bits.prediction.bits.entry
// we'd prefer PseudoLRU replacement, but it only works for powers of 2 val nextRepl = Counter(r_btb_update.valid && !updateHit, entries)._1
val nextRepl =
if (!isPow2(entries)) {
Counter(r_btb_update.valid && !updateHit, entries)._1
} else {
val plru = new PseudoLRU(entries)
when (hits.orR) { plru.access(OHToUInt(hits)) }
plru.replace
}
val useUpdatePageHit = updatePageHit.orR val useUpdatePageHit = updatePageHit.orR
val usePageHit = pageHit.orR val usePageHit = pageHit.orR