riscv/rocket-chip
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Fix groundtest to provide missing signals to TLB

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This commit is contained in:
Andrew Waterman 2017-03-26 11:30:11 -07:00 committed by Andrew Waterman
parent 5d1165c850
commit 7180352067
2 changed files with 3 additions and 5 deletions
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2
riscv-tools

@ -1 +1 @@
Subproject commit 24ce6c0870755bd2af1bc39887ab84684c5ce586
Subproject commit 4f430b184ed07890cd30ad144ded6d7cb07dcdf0

6
src/main/scala/groundtest/DummyPTW.scala
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@ -33,6 +33,7 @@ class DummyPTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
val s2_resp = Wire(new PTWResp)
s2_resp.pte.ppn := s2_ppn
s2_resp.pte.reserved_for_software := UInt(0)
s2_resp.level := UInt(pgLevels-1)
s2_resp.pte.d := Bool(true)
s2_resp.pte.a := Bool(true)
s2_resp.pte.g := Bool(false)
@ -45,10 +46,7 @@ class DummyPTW(n: Int)(implicit p: Parameters) extends CoreModule()(p) {
io.requestors.zipWithIndex.foreach { case (requestor, i) =>
requestor.resp.valid := s2_valid && s2_chosen === UInt(i)
requestor.resp.bits := s2_resp
requestor.status.prv := UInt(PRV.S)
requestor.status.debug := Bool(false)
requestor.status.mprv := Bool(true)
requestor.status.mpp := UInt(0)
requestor.status := 0.U.asTypeOf(requestor.status)
requestor.ptbr.mode := requestor.ptbr.pgLevelsToMode(pgLevels).U
requestor.ptbr.asid := UInt(0)
requestor.ptbr.ppn := UInt(0)