riscv/rocket-chip
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fix for flushed div/mul instructions

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This commit is contained in:
Rimas Avizienis 2011-11-07 01:03:47 -08:00
parent 9d63087eb2
commit 7130edac8d
1 changed files with 2 additions and 2 deletions
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4
rocket/src/main/scala/dpath.scala
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@ -312,7 +312,7 @@ class rocketDpath extends Component
// divider // divider
div.io.div_fn := ex_reg_ctrl_div_fn; div.io.div_fn := ex_reg_ctrl_div_fn;
div.io.div_val := ex_reg_ctrl_div_val; div.io.div_val := ex_reg_ctrl_div_val && !io.ctrl.killx;
div.io.div_waddr := ex_reg_waddr; div.io.div_waddr := ex_reg_waddr;
div.io.dpath_rs1 := ex_reg_rs1; div.io.dpath_rs1 := ex_reg_rs1;
div.io.dpath_rs2 := ex_reg_rs2; div.io.dpath_rs2 := ex_reg_rs2;
@ -322,7 +322,7 @@ class rocketDpath extends Component
io.ctrl.div_result_val := div.io.div_result_val; io.ctrl.div_result_val := div.io.div_result_val;
// multiplier // multiplier
mul.io.mul_val := ex_reg_ctrl_mul_val; mul.io.mul_val := ex_reg_ctrl_mul_val && !io.ctrl.killx;
mul.io.mul_fn := ex_reg_ctrl_mul_fn; mul.io.mul_fn := ex_reg_ctrl_mul_fn;
mul.io.mul_tag := ex_reg_waddr; mul.io.mul_tag := ex_reg_waddr;
mul.io.in0 := ex_reg_rs1; mul.io.in0 := ex_reg_rs1;