riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Move BootROM from Coreplex to Periphery

Browse Source
This commit is contained in:
Yunsup Lee
2016-09-14 16:09:59 -07:00
parent f7121a2a5b
commit 710f1ec020
5 changed files with 53 additions and 33 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/rocketchip/Top.scala
View File

@ -75,17 +75,17 @@ class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L,
/** Example Top with Periphery */
class ExampleTop(p: Parameters) extends BaseTop(p)
with PeripheryDebug with PeripheryExtInterrupts with PeripheryAON
with PeripheryBootROM with PeripheryDebug with PeripheryExtInterrupts with PeripheryAON
with PeripheryMasterMem with PeripheryMasterMMIO with PeripherySlave {
override lazy val module = Module(new ExampleTopModule(p, this, new ExampleTopBundle(p, _)))
}
class ExampleTopBundle(p: Parameters, c: Coreplex) extends BaseTopBundle(p, c)
with PeripheryDebugBundle with PeripheryExtInterruptsBundle with PeripheryAONBundle
with PeripheryBootROMBundle with PeripheryDebugBundle with PeripheryExtInterruptsBundle with PeripheryAONBundle
with PeripheryMasterMemBundle with PeripheryMasterMMIOBundle with PeripherySlaveBundle
class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle](p: Parameters, l: L, b: Coreplex => B) extends BaseTopModule(p, l, b)
with PeripheryDebugModule with PeripheryExtInterruptsModule with PeripheryAONModule
with PeripheryBootROMModule with PeripheryDebugModule with PeripheryExtInterruptsModule with PeripheryAONModule
with PeripheryMasterMemModule with PeripheryMasterMMIOModule with PeripherySlaveModule
/** Example Top with TestRAM */