riscv/rocket-chip
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Move BootROM from Coreplex to Periphery

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This commit is contained in:
Yunsup Lee
2016-09-14 16:09:59 -07:00
parent f7121a2a5b
commit 710f1ec020
5 changed files with 53 additions and 33 deletions
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23
src/main/scala/rocketchip/Periphery.scala
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@ -303,6 +303,29 @@ trait PeripheryAONModule extends HasPeripheryParameters {
/////
trait PeripheryBootROM extends LazyModule {
implicit val p: Parameters
val pDevices: ResourceManager[AddrMapEntry]
pDevices.add(AddrMapEntry("bootrom", MemRange(0x1000, 4096, MemAttr(AddrMapProt.RX))))
}
trait PeripheryBootROMBundle {
implicit val p: Parameters
}
trait PeripheryBootROMModule extends HasPeripheryParameters {
implicit val p: Parameters
val outer: PeripheryBootROM
val io: PeripheryBootROMBundle
val mmioNetwork: Option[TileLinkRecursiveInterconnect]
val bootROM = Module(new ROMSlave(GenerateBootROM(p))(innerMMIOParams))
bootROM.io <> mmioNetwork.get.port("bootrom")
}
/////
trait PeripheryTestRAM extends LazyModule {
implicit val p: Parameters
val pDevices: ResourceManager[AddrMapEntry]