riscv/rocket-chip
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Move BootROM from Coreplex to Periphery

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This commit is contained in:
Yunsup Lee
2016-09-14 16:09:59 -07:00
parent f7121a2a5b
commit 710f1ec020
5 changed files with 53 additions and 33 deletions
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2
src/main/scala/groundtest/Regression.scala
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@ -72,7 +72,7 @@ class IOGetAfterPutBlockRegression(implicit p: Parameters) extends Regression()(
io.mem.grant.ready := Bool(true)
io.cache.req.valid := !get_sent && started
io.cache.req.bits.addr := UInt(addrMap("io:int:bootrom").start)
io.cache.req.bits.addr := UInt(addrMap("io:ext:bootrom").start)
io.cache.req.bits.typ := UInt(log2Ceil(32 / 8))
io.cache.req.bits.cmd := M_XRD
io.cache.req.bits.tag := UInt(0)