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Factor out some of HaveRocketTiles into HaveTiles

This commit is contained in:
Andrew Waterman 2017-10-06 00:56:23 -07:00
parent 34e96c03b1
commit 70a4127cb8
4 changed files with 24 additions and 14 deletions

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@ -6,6 +6,9 @@ import Chisel._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.tile.{BaseTile, TileParams}
import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
import freechips.rocketchip.util._
/** Enumerates the three types of clock crossing between tiles and system bus */
@ -29,6 +32,21 @@ abstract class BareCoreplexModule[+L <: BareCoreplex](_outer: L) extends LazyMod
println(outer.dts)
}
trait HasTiles extends HasSystemBus {
protected def tileParams: Seq[TileParams]
def nRocketTiles = tileParams.size
def hartIdList = tileParams.map(_.hartid)
// Handle interrupts to be routed directly into each tile
// TODO: figure out how to merge the localIntNodes and coreIntXbar
def localIntCounts = tileParams.map(_.core.nLocalInterrupts)
def localIntNodes = tileParams map { t =>
(t.core.nLocalInterrupts > 0).option(LazyModule(new IntXbar).intnode)
}
val rocket_tiles: Seq[BaseTile]
}
/** Base Coreplex class with no peripheral devices or ports added */
abstract class BaseCoreplex(implicit p: Parameters) extends BareCoreplex
with HasInterruptBus

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@ -14,7 +14,7 @@ import freechips.rocketchip.util._
case object RocketTilesKey extends Field[Seq[RocketTileParams]](Nil)
case object RocketCrossing extends Field[CoreplexClockCrossing](SynchronousCrossing())
trait HasRocketTiles extends HasSystemBus
trait HasRocketTiles extends HasTiles
with HasPeripheryBus
with HasPeripheryPLIC
with HasPeripheryClint
@ -22,21 +22,11 @@ trait HasRocketTiles extends HasSystemBus
val module: HasRocketTilesModuleImp
private val crossing = p(RocketCrossing)
private val tileParams = p(RocketTilesKey)
val nRocketTiles = tileParams.size
val hartIdList = tileParams.map(_.hartid)
// Handle interrupts to be routed directly into each tile
// TODO: figure out how to merge the localIntNodes and coreIntXbar below
val localIntCounts = tileParams.map(_.core.nLocalInterrupts)
val localIntNodes = tileParams map { t =>
(t.core.nLocalInterrupts > 0).option(LazyModule(new IntXbar).intnode)
}
protected val tileParams = p(RocketTilesKey)
// Make a wrapper for each tile that will wire it to coreplex devices and crossbars,
// according to the specified type of clock crossing.
val wiringTuple = localIntNodes.zip(tileParams)
val rocket_tiles: Seq[BaseTile] = wiringTuple.map { case (lip, tp) =>
val rocket_tiles: Seq[BaseTile] = localIntNodes.zip(tileParams).map { case (lip, tp) =>
val pWithExtra = p.alterPartial {
case TileKey => tp
case BuildRoCC => tp.rocc
@ -107,7 +97,7 @@ trait HasRocketTilesModuleImp extends LazyModuleImp
with HasRocketTilesBundle
with HasResetVectorWire
with HasPeripheryDebugModuleImp {
val outer: HasRocketTiles
val outer: HasTiles with HasPeripheryDebug
def resetVectorBits: Int = {
// Consider using the minimum over all widths, rather than enforcing homogeneity

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@ -65,6 +65,7 @@ case class TraceGenParams(
memStart: BigInt, //p(ExtMem).base
numGens: Int) extends GroundTestTileParams {
def build(i: Int, p: Parameters): GroundTestTile = new TraceGenTile(i, this)(p)
val hartid = 0
val trace = false
}

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@ -22,6 +22,7 @@ trait TileParams {
val rocc: Seq[RoCCParams]
val btb: Option[BTBParams]
val trace: Boolean
val hartid: Int
}
trait HasTileParameters {