riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tilelink2: disable A=>D bypass in ToAXI4 whenever possible

Browse Source
This commit is contained in:
Wesley W. Terpstra 2017-01-23 18:03:29 -08:00
parent 64e1de751d
commit 6ff35a387a
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/main/scala/uncore/tilelink2/ToAXI4.scala
View File

@ -127,7 +127,8 @@ class TLToAXI4(idBits: Int, combinational: Boolean = true)(implicit p: Parameter
// We know there can only be as many outstanding requests as TL sources
// However, AXI read and write queues are not mutually FIFO.
// Therefore, we want to pop them individually, but share the storage.
PositionalMultiQueue(UInt(width=max(1,bankBits)), positions=bankEntries(i), ways=2, combinational=combinational)
val bypass = combinational && edgeOut.slave.minLatency == 0
PositionalMultiQueue(UInt(width=max(1,bankBits)), positions=bankEntries(i), ways=2, combinational=bypass)
}
val a_bankPosition = if (posBits == 0) UInt(0) else a_source(sourceBits-1, idBits)