riscv/rocket-chip
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add atomic and prefetch drivers

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This commit is contained in:
Howard Mao 2016-07-15 16:37:33 -07:00
parent 2ec736ed67
commit 6fc4236782
2 changed files with 85 additions and 2 deletions
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79
groundtest/src/main/scala/unittests/Drivers.scala
View File

@ -306,6 +306,85 @@ class PutBlockSweepDriver(val n: Int)(implicit p: Parameters)
"PutBlockSweep: data does not match expected")
}
class PutAtomicDriver(implicit p: Parameters) extends Driver()(p) {
val s_idle :: s_put :: s_atomic :: s_get :: s_done :: Nil = Enum(Bits(), 5)
val state = Reg(init = s_idle)
val sending = Reg(init = Bool(false))
val put_acquire = Put(
client_xact_id = UInt(0),
addr_block = UInt(0),
addr_beat = UInt(0),
// Put 15 in bytes 3:2
data = UInt(15 << 16),
wmask = Some(UInt(0x0c)))
val amo_acquire = PutAtomic(
client_xact_id = UInt(0),
addr_block = UInt(0),
addr_beat = UInt(0),
addr_byte = UInt(2),
atomic_opcode = M_XA_ADD,
operand_size = MT_H,
data = UInt(3 << 16))
val get_acquire = Get(
client_xact_id = UInt(0),
addr_block = UInt(0),
addr_beat = UInt(0))
io.finished := (state === s_done)
io.mem.acquire.valid := sending
io.mem.acquire.bits := MuxLookup(state, get_acquire, Seq(
s_put -> put_acquire,
s_atomic -> amo_acquire,
s_get -> get_acquire))
io.mem.grant.ready := !sending
when (io.mem.acquire.fire()) { sending := Bool(false) }
when (state === s_idle && io.start) {
state := s_put
sending := Bool(true)
}
when (io.mem.grant.fire()) {
when (state === s_put) { sending := Bool(true); state := s_atomic }
when (state === s_atomic) { sending := Bool(true); state := s_get }
when (state === s_get) { state := s_done }
}
assert(!io.mem.grant.valid || !io.mem.grant.bits.hasData() ||
io.mem.grant.bits.data(31, 16) === UInt(18))
}
class PrefetchDriver(implicit p: Parameters) extends Driver()(p) {
val s_idle :: s_put_pf :: s_get_pf :: s_done :: Nil = Enum(Bits(), 4)
val state = Reg(init = s_idle)
val sending = Reg(init = Bool(false))
when (state === s_idle) {
sending := Bool(true)
state := s_put_pf
}
when (io.mem.acquire.fire()) { sending := Bool(false) }
when (io.mem.grant.fire()) {
when (state === s_put_pf) { sending := Bool(true); state := s_get_pf }
when (state === s_get_pf) { state := s_done }
}
io.finished := (state === s_done)
io.mem.acquire.valid := sending
io.mem.acquire.bits := Mux(state === s_put_pf,
PutPrefetch(
client_xact_id = UInt(0),
addr_block = UInt(0)),
GetPrefetch(
client_xact_id = UInt(0),
addr_block = UInt(0)))
io.mem.grant.ready := !sending
}
class DriverSet(driverGen: Parameters => Seq[Driver])(implicit p: Parameters)
extends Driver()(p) {
val s_start :: s_run :: s_done :: Nil = Enum(Bits(), 3)

8
groundtest/src/main/scala/unittests/TileLink.scala
View File

@ -26,7 +26,8 @@ class SmiConverterTest(implicit val p: Parameters) extends UnitTest
Seq(
Module(new PutSweepDriver(tlDepth)),
Module(new PutMaskDriver(smiWidth / 8)),
Module(new PutBlockSweepDriver(tlDepth / tlDataBeats)))
Module(new PutBlockSweepDriver(tlDepth / tlDataBeats)),
Module(new GetMultiWidthDriver))
})(outermostParams))
conv.io.tl <> driver.io.mem
@ -66,7 +67,10 @@ class TileLinkRAMTest(implicit val p: Parameters)
Seq(
Module(new PutSweepDriver(depth)),
Module(new PutMaskDriver),
Module(new PutBlockSweepDriver(depth / tlDataBeats)))
Module(new PutAtomicDriver),
Module(new PutBlockSweepDriver(depth / tlDataBeats)),
Module(new PrefetchDriver),
Module(new GetMultiWidthDriver))
}))
ram.io <> driver.io.mem
driver.io.start := io.start