riscv/rocket-chip
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Improve Seq indexing QoR

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Andrew Waterman 2017-04-13 15:54:24 -07:00 committed by Andrew Waterman
parent d203c4c654
commit 6fbbccca3e
2 changed files with 9 additions and 6 deletions
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2
src/main/scala/rocket/Rocket.scala
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@ -254,7 +254,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
val id_bypass_src = id_raddr.map(raddr => bypass_sources.map(s => s._1 && s._2 === raddr))
// execute stage
val bypass_mux = Vec(bypass_sources.map(_._3))
val bypass_mux = bypass_sources.map(_._3)
val ex_reg_rs_bypass = Reg(Vec(id_raddr.size, Bool()))
val ex_reg_rs_lsb = Reg(Vec(id_raddr.size, UInt(width = log2Ceil(bypass_sources.size))))
val ex_reg_rs_msb = Reg(Vec(id_raddr.size, UInt()))

13
src/main/scala/util/Package.scala
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@ -11,12 +11,15 @@ package object util {
implicit class SeqToAugmentedSeq[T <: Data](val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size == 1) {
x.head
if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
val half = 1 << (log2Ceil(x.size) - 1)
val newIdx = idx & UInt(half - 1)
Mux(idx >= UInt(half), x.drop(half)(newIdx), x.take(half)(newIdx))
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | UInt(0, log2Ceil(x.size)))(log2Ceil(x.size)-1, 0)
(x.head /: x.zipWithIndex.tail) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}