riscv/rocket-chip
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Improve Seq indexing QoR

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Andrew Waterman authored and Andrew Waterman committed 2017-04-14 01:03:11 -07:00
1 parent d203c4c654
commit 6fbbccca3e
2 files changed
+9 -6
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src/main/scala/rocket/Rocket.scala
+1 -1
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@@ -254,7 +254,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
val id_bypass_src = id_raddr.map(raddr => bypass_sources.map(s => s._1 && s._2 === raddr))
// execute stage
val bypass_mux = Vec(bypass_sources.map(_._3))
val bypass_mux = bypass_sources.map(_._3)
val ex_reg_rs_bypass = Reg(Vec(id_raddr.size, Bool()))
val ex_reg_rs_lsb = Reg(Vec(id_raddr.size, UInt(width = log2Ceil(bypass_sources.size))))
val ex_reg_rs_msb = Reg(Vec(id_raddr.size, UInt()))