riscv/rocket-chip
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Minor refactor of StoreGen/AMOALU.

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This commit is contained in:
Henry Cook 2015-10-16 19:12:21 -07:00
parent 1441590c3b
commit 6f8997bee9
1 changed files with 3 additions and 3 deletions
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6
rocket/src/main/scala/nbdcache.scala
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@ -161,8 +161,8 @@ class IOMSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val req_cmd_sc = req.cmd === M_XSC val req_cmd_sc = req.cmd === M_XSC
val grant_word = Reg(UInt(width = wordBits)) val grant_word = Reg(UInt(width = wordBits))
val storegen = new StoreGen(req.typ, req.addr, req.data) val storegen = new StoreGen64(req.typ, req.addr, req.data)
val loadgen = new LoadGen(req.typ, req.addr, grant_word, req_cmd_sc) val loadgen = new LoadGen64(req.typ, req.addr, grant_word, req_cmd_sc)
val beat_offset = req.addr(beatOffBits - 1, wordOffBits) val beat_offset = req.addr(beatOffBits - 1, wordOffBits)
val beat_mask = (storegen.mask << Cat(beat_offset, UInt(0, wordOffBits))) val beat_mask = (storegen.mask << Cat(beat_offset, UInt(0, wordOffBits)))
@ -992,7 +992,7 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
// load data subword mux/sign extension // load data subword mux/sign extension
val s2_data_word_prebypass = s2_data_uncorrected >> Cat(s2_word_idx, Bits(0,log2Up(coreDataBits))) val s2_data_word_prebypass = s2_data_uncorrected >> Cat(s2_word_idx, Bits(0,log2Up(coreDataBits)))
val s2_data_word = Mux(s2_store_bypass, s2_store_bypass_data, s2_data_word_prebypass) val s2_data_word = Mux(s2_store_bypass, s2_store_bypass_data, s2_data_word_prebypass)
val loadgen = new LoadGen(s2_req.typ, s2_req.addr, s2_data_word, s2_sc) val loadgen = new LoadGen64(s2_req.typ, s2_req.addr, s2_data_word, s2_sc)
amoalu.io.addr := s2_req.addr amoalu.io.addr := s2_req.addr
amoalu.io.cmd := s2_req.cmd amoalu.io.cmd := s2_req.cmd