From 6f3a4cd73380edbd20d266915a8a2d7f346bd030 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Tue, 10 Oct 2017 23:42:55 -0700 Subject: [PATCH] build: pass annotations to firrtl --- emulator/Makefrag-verilator | 2 +- vsim/Makefrag-verilog | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/emulator/Makefrag-verilator b/emulator/Makefrag-verilator index 6b51e63c..021e131c 100644 --- a/emulator/Makefrag-verilator +++ b/emulator/Makefrag-verilator @@ -14,7 +14,7 @@ $(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(boot %.v %.conf: %.fir $(FIRRTL_JAR) mkdir -p $(dir $@) - $(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $*.v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$*.conf + $(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $*.v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$*.conf -faf $*.anno -ffaaf $(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf $(VLSI_MEM_GEN) cd $(generated_dir) && \ diff --git a/vsim/Makefrag-verilog b/vsim/Makefrag-verilog index 8ac71ce4..d0571eeb 100644 --- a/vsim/Makefrag-verilog +++ b/vsim/Makefrag-verilog @@ -14,7 +14,7 @@ $(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(boot $(generated_dir)/%.v $(generated_dir)/%.conf: $(generated_dir)/%.fir $(FIRRTL_JAR) mkdir -p $(dir $@) - $(FIRRTL) -i $< -o $(generated_dir)/$*.v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$(generated_dir)/$*.conf + $(FIRRTL) -i $< -o $(generated_dir)/$*.v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$(generated_dir)/$*.conf -faf $(generated_dir)/$*.anno -ffaaf $(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf $(mem_gen) cd $(generated_dir) && \