riscv/rocket-chip
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tilelink: add mask rom

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Yunsup Lee committed 2017-07-31 21:34:04 -07:00
1 parent 4b33249812
commit 6ef8ee5d4d
10 files changed
+312 -55
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vsim/Makefile
+1 -1
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@@ -11,7 +11,7 @@ default: all
base_dir = $(abspath ..)
generated_dir = $(abspath ./generated-src)
VLSI_MEM_GEN ?= $(base_dir)/vsim/vlsi_mem_gen
VLSI_MEM_GEN ?= $(base_dir)/scripts/vlsi_mem_gen
mem_gen = $(VLSI_MEM_GEN)
sim_dir = .
output_dir = $(sim_dir)/output