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tilelink: add mask rom

This commit is contained in:
Yunsup Lee
2017-07-31 21:12:45 -07:00
parent 4b33249812
commit 6ef8ee5d4d
10 changed files with 312 additions and 55 deletions

View File

@ -53,6 +53,21 @@ trait HasGeneratorUtilities {
Driver.elaborate(gen)
}
def enumerateROMs(circuit: Circuit): String = {
val res = new StringBuilder
val configs =
circuit.components flatMap { m =>
m.id match {
case rom: BlackBoxedROM => Some((rom.name, ROMGenerator.lookup(rom)))
case _ => None
}
}
configs foreach { case (name, c) =>
res append s"name ${name} depth ${c.depth} width ${c.width}\n"
}
res.toString
}
def writeOutputFile(targetDir: String, fname: String, contents: String): File = {
val f = new File(targetDir, fname)
val fw = new FileWriter(f)
@ -103,6 +118,10 @@ trait GeneratorApp extends App with HasGeneratorUtilities {
TestGeneration.addSuite(DefaultTestSuites.singleRegression)
}
def generateROMs {
writeOutputFile(td, s"$longName.rom.conf", enumerateROMs(circuit))
}
/** Output files created as a side-effect of elaboration */
def generateArtefacts {
ElaborationArtefacts.files.foreach { case (extension, contents) =>

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@ -0,0 +1,35 @@
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import Chisel._
import scala.collection.mutable.{HashMap}
case class ROMConfig(name: String, depth: Int, width: Int)
class BlackBoxedROM(c: ROMConfig) extends BlackBox {
val io = new Bundle {
val clock = Clock(INPUT)
val address = UInt(INPUT, log2Ceil(c.depth))
val oe = Bool(INPUT)
val me = Bool(INPUT)
val q = UInt(OUTPUT, c.width)
}
override def desiredName: String = c.name
}
object ROMGenerator {
private var finalized = false
private val roms = HashMap[BlackBoxedROM, ROMConfig]()
def apply(c: ROMConfig): BlackBoxedROM = {
require(!finalized)
val m = Module(new BlackBoxedROM(c))
roms(m) = c
m
}
def lookup(m: BlackBoxedROM): ROMConfig = {
finalized = true
roms(m)
}
}