tilelink: add mask rom
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@ -53,6 +53,21 @@ trait HasGeneratorUtilities {
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Driver.elaborate(gen)
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}
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def enumerateROMs(circuit: Circuit): String = {
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val res = new StringBuilder
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val configs =
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circuit.components flatMap { m =>
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m.id match {
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case rom: BlackBoxedROM => Some((rom.name, ROMGenerator.lookup(rom)))
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case _ => None
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}
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}
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configs foreach { case (name, c) =>
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res append s"name ${name} depth ${c.depth} width ${c.width}\n"
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}
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res.toString
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}
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def writeOutputFile(targetDir: String, fname: String, contents: String): File = {
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val f = new File(targetDir, fname)
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val fw = new FileWriter(f)
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@ -103,6 +118,10 @@ trait GeneratorApp extends App with HasGeneratorUtilities {
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TestGeneration.addSuite(DefaultTestSuites.singleRegression)
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}
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def generateROMs {
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writeOutputFile(td, s"$longName.rom.conf", enumerateROMs(circuit))
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}
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/** Output files created as a side-effect of elaboration */
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def generateArtefacts {
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ElaborationArtefacts.files.foreach { case (extension, contents) =>
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35
src/main/scala/util/ROMGenerator.scala
Normal file
35
src/main/scala/util/ROMGenerator.scala
Normal file
@ -0,0 +1,35 @@
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// See LICENSE.SiFive for license details.
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package freechips.rocketchip.util
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import Chisel._
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import scala.collection.mutable.{HashMap}
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case class ROMConfig(name: String, depth: Int, width: Int)
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class BlackBoxedROM(c: ROMConfig) extends BlackBox {
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val io = new Bundle {
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val clock = Clock(INPUT)
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val address = UInt(INPUT, log2Ceil(c.depth))
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val oe = Bool(INPUT)
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val me = Bool(INPUT)
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val q = UInt(OUTPUT, c.width)
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}
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override def desiredName: String = c.name
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}
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object ROMGenerator {
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private var finalized = false
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private val roms = HashMap[BlackBoxedROM, ROMConfig]()
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def apply(c: ROMConfig): BlackBoxedROM = {
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require(!finalized)
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val m = Module(new BlackBoxedROM(c))
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roms(m) = c
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m
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}
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def lookup(m: BlackBoxedROM): ROMConfig = {
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finalized = true
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roms(m)
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}
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}
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