tilelink: add mask rom

src/main/scala/devices/tilelink/BootROM.scala

@@ -6,6 +6,9 @@ import Chisel._
 import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.coreplex._
 import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util._
+
 import java.nio.{ByteBuffer, ByteOrder}
 import java.nio.file.{Files, Paths}
 
@@ -17,6 +20,47 @@ case class BootROMParams(
   contentFileName: String)
 case object BootROMParams extends Field[BootROMParams]
 
+class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4,
+  resources: Seq[Resource] = new SimpleDevice("rom", Seq("sifive,rom0")).reg("mem"))(implicit p: Parameters) extends LazyModule
+{
+  val node = TLManagerNode(beatBytes, TLManagerParameters (
+    address     = List(AddressSet(base, size-1)),
+    resources   = resources,
+    regionType  = RegionType.UNCACHED,
+    executable  = executable,
+    supportsGet = TransferSizes(1, beatBytes),
+    fifoId      = Some(0)))
+
+  lazy val module = new LazyModuleImp(this) {
+    val io = new Bundle {
+      val in = node.bundleIn
+    }
+
+    val contents = contentsDelayed
+    val wrapSize = 1 << log2Ceil(contents.size)
+    require (wrapSize <= size)
+
+    val in = io.in(0)
+    val edge = node.edgesIn(0)
+
+    val words = (contents ++ Seq.fill(wrapSize-contents.size)(0.toByte)).grouped(beatBytes).toSeq
+    val bigs = words.map(_.foldRight(BigInt(0)){ case (x,y) => (x.toInt & 0xff) | y << 8})
+    val rom = Vec(bigs.map(x => UInt(x, width = 8*beatBytes)))
+
+    in.d.valid := in.a.valid
+    in.a.ready := in.d.ready
+
+    val index = in.a.bits.address(log2Ceil(wrapSize)-1,log2Ceil(beatBytes))
+    val high = if (wrapSize == size) UInt(0) else in.a.bits.address(log2Ceil(size)-1, log2Ceil(wrapSize))
+    in.d.bits := edge.AccessAck(in.a.bits, Mux(high.orR, UInt(0), rom(index)))
+
+    // Tie off unused channels
+    in.b.valid := Bool(false)
+    in.c.ready := Bool(true)
+    in.e.ready := Bool(true)
+  }
+}
+
 /** Adds a boot ROM that contains the DTB describing the system's coreplex. */
 trait HasPeripheryBootROM extends HasPeripheryBus {
   val dtb: DTB

src/main/scala/devices/tilelink/MaskROM.scala

@@ -0,0 +1,71 @@
+// See LICENSE.SiFive for license details.
+
+package freechips.rocketchip.devices.tilelink
+
+import Chisel._
+import freechips.rocketchip.coreplex.{HasPeripheryBus}
+import freechips.rocketchip.config.{Field, Parameters}
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util._
+
+case class MaskROMParams(address: BigInt, name: String, depth: Int = 2048, width: Int = 32)
+
+case object PeripheryMaskROMKey extends Field[Seq[MaskROMParams]]
+
+trait HasPeripheryMaskROMSlave extends HasPeripheryBus {
+  val maskROMParams = p(PeripheryMaskROMKey)
+  val maskROMs = maskROMParams map { params =>
+    val maskROM = LazyModule(new TLMaskROM(params))
+    maskROM.node := pbus.toFixedWidthSingleBeatSlave(maskROM.beatBytes)
+    maskROM
+  }
+}
+
+class TLMaskROM(c: MaskROMParams)(implicit p: Parameters) extends LazyModule {
+  val beatBytes = c.width/8
+  val node = TLManagerNode(beatBytes, TLManagerParameters(
+    address            = AddressSet.misaligned(c.address, c.depth*beatBytes),
+    resources          = new SimpleDevice("rom", Seq("sifive,maskrom0")).reg("mem"),
+    regionType         = RegionType.UNCACHED,
+    executable         = true,
+    supportsGet        = TransferSizes(1, beatBytes),
+    fifoId             = Some(0))) // requests are handled in order
+
+  lazy val module = new LazyModuleImp(this) {
+    val io = new Bundle {
+      val in = node.bundleIn
+    }
+
+    val in = io.in(0)
+    val edge = node.edgesIn(0)
+
+    val rom = ROMGenerator(ROMConfig(c.name, c.depth, c.width))
+    rom.io.clock := clock
+    rom.io.address := edge.addr_hi(in.a.bits.address - UInt(c.address))(log2Ceil(c.depth)-1, 0)
+    rom.io.oe := Bool(true) // active high tri state enable
+    rom.io.me := in.a.fire()
+
+    val d_full = RegInit(Bool(false))
+    val d_size = Reg(UInt())
+    val d_source = Reg(UInt())
+
+    // Flow control
+    when (in.d.fire()) { d_full := Bool(false) }
+    when (in.a.fire()) { d_full := Bool(true)  }
+    in.d.valid := d_full
+    in.a.ready := in.d.ready || !d_full
+
+    when (in.a.fire()) {
+      d_size   := in.a.bits.size
+      d_source := in.a.bits.source
+    }
+
+    in.d.bits := edge.AccessAck(d_source, d_size, rom.io.q)
+
+    // Tie off unused channels
+    in.b.valid := Bool(false)
+    in.c.ready := Bool(true)
+    in.e.ready := Bool(true)
+  }
+}

src/main/scala/devices/tilelink/ROM.scala

@@ -1,52 +0,0 @@
-// See LICENSE.SiFive for license details.
-// See LICENSE.Berkeley for license details.
-
-package freechips.rocketchip.devices.tilelink
-
-import Chisel._
-import freechips.rocketchip.config.Parameters
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.tilelink._
-import freechips.rocketchip.util._
-
-class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4,
-  resources: Seq[Resource] = new SimpleDevice("rom", Seq("sifive,rom0")).reg("mem"))(implicit p: Parameters) extends LazyModule
-{
-
-  val node = TLManagerNode(beatBytes, TLManagerParameters (
-    address     = List(AddressSet(base, size-1)),
-    resources   = resources,
-    regionType  = RegionType.UNCACHED,
-    executable  = executable,
-    supportsGet = TransferSizes(1, beatBytes),
-    fifoId      = Some(0)))
-
-  lazy val module = new LazyModuleImp(this) {
-    val io = new Bundle {
-      val in = node.bundleIn
-    }
-
-    val contents = contentsDelayed
-    val wrapSize = 1 << log2Ceil(contents.size)
-    require (wrapSize <= size)
-
-    val in = io.in(0)
-    val edge = node.edgesIn(0)
-
-    val words = (contents ++ Seq.fill(wrapSize-contents.size)(0.toByte)).grouped(beatBytes).toSeq
-    val bigs = words.map(_.foldRight(BigInt(0)){ case (x,y) => (x.toInt & 0xff) | y << 8})
-    val rom = Vec(bigs.map(x => UInt(x, width = 8*beatBytes)))
-
-    in.d.valid := in.a.valid
-    in.a.ready := in.d.ready
-
-    val index = in.a.bits.address(log2Ceil(wrapSize)-1,log2Ceil(beatBytes))
-    val high = if (wrapSize == size) UInt(0) else in.a.bits.address(log2Ceil(size)-1, log2Ceil(wrapSize))
-    in.d.bits := edge.AccessAck(in.a.bits, Mux(high.orR, UInt(0), rom(index)))
-
-    // Tie off unused channels
-    in.b.valid := Bool(false)
-    in.c.ready := Bool(true)
-    in.e.ready := Bool(true)
-  }
-}