tilelink: add mask rom
This commit is contained in:
Yunsup Lee
178
scripts/vlsi_mem_gen
Executable file
178
scripts/vlsi_mem_gen
Executable file
@ -0,0 +1,178 @@
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#! /usr/bin/env python
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# See LICENSE.SiFive for license details.
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# See LICENSE.Berkeley for license details.
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import sys
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import math
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use_latches = 0
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def parse_line(line):
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name = ''
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width = 0
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depth = 0
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ports = ''
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mask_gran = 0
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tokens = line.split()
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i = 0
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for i in range(0,len(tokens),2):
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s = tokens[i]
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if s == 'name':
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name = tokens[i+1]
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elif s == 'width':
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width = int(tokens[i+1])
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mask_gran = width # default setting
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elif s == 'depth':
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depth = int(tokens[i+1])
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elif s == 'ports':
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ports = tokens[i+1].split(',')
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elif s == 'mask_gran':
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mask_gran = int(tokens[i+1])
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else:
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sys.exit('%s: unknown argument %s' % (sys.argv[0], a))
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return (name, width, depth, mask_gran, width//mask_gran, ports)
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def gen_mem(name, width, depth, mask_gran, mask_seg, ports):
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addr_width = max(math.ceil(math.log(depth)/math.log(2)),1)
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port_spec = []
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readports = []
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writeports = []
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latchports = []
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rwports = []
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decl = []
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combinational = []
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sequential = []
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maskedports = {}
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for pid in range(len(ports)):
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ptype = ports[pid]
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if ptype[0:1] == 'm':
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ptype = ptype[1:]
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maskedports[pid] = pid
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if ptype == 'read':
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prefix = 'R%d_' % len(readports)
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port_spec.append('input %sclk' % prefix)
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port_spec.append('input [%d:0] %saddr' % (addr_width-1, prefix))
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port_spec.append('input %sen' % prefix)
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port_spec.append('output [%d:0] %sdata' % (width-1, prefix))
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readports.append(pid)
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elif ptype == 'write':
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prefix = 'W%d_' % len(writeports)
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port_spec.append('input %sclk' % prefix)
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port_spec.append('input [%d:0] %saddr' % (addr_width-1, prefix))
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port_spec.append('input %sen' % prefix)
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port_spec.append('input [%d:0] %sdata' % (width-1, prefix))
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if pid in maskedports:
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port_spec.append('input [%d:0] %smask' % (mask_seg-1, prefix))
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if not use_latches or pid in maskedports:
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writeports.append(pid)
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else:
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latchports.append(pid)
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elif ptype == 'rw':
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prefix = 'RW%d_' % len(rwports)
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port_spec.append('input %sclk' % prefix)
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port_spec.append('input [%d:0] %saddr' % (addr_width-1, prefix))
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port_spec.append('input %sen' % prefix)
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port_spec.append('input %swmode' % prefix)
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if pid in maskedports:
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port_spec.append('input [%d:0] %swmask' % (mask_seg-1, prefix))
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port_spec.append('input [%d:0] %swdata' % (width-1, prefix))
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port_spec.append('output [%d:0] %srdata' % (width-1, prefix))
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rwports.append(pid)
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else:
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sys.exit('%s: unknown port type %s' % (sys.argv[0], ptype))
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nr = len(readports)
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nw = len(writeports)
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nrw = len(rwports)
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masked = len(maskedports)>0
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tup = (depth, width, nr, nw, nrw, masked)
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for idx in range(nr):
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prefix = 'R%d_' % idx
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decl.append('reg [%d:0] reg_%saddr;' % (addr_width-1, prefix))
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sequential.append('always @(posedge %sclk)' % prefix)
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sequential.append(' if (%sen) reg_%saddr <= %saddr;' % (prefix, prefix, prefix))
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combinational.append('assign %sdata = ram[reg_%saddr];' % (prefix, prefix))
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for idx in range(nrw):
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prefix = 'RW%d_' % idx
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decl.append('reg [%d:0] reg_%saddr;' % (addr_width-1, prefix))
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sequential.append('always @(posedge %sclk)' % prefix)
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sequential.append(' if (%sen && !%swmode) reg_%saddr <= %saddr;' % (prefix, prefix, prefix, prefix))
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combinational.append('assign %srdata = ram[reg_%saddr];' % (prefix, prefix))
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for idx in range(len(latchports)):
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prefix = 'W%d_' % idx
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decl.append('reg [%d:0] latch_%saddr;' % (addr_width-1, prefix))
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decl.append('reg [%d:0] latch_%sdata;' % (width-1, prefix))
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decl.append('reg latch_%sen;' % (prefix))
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combinational.append('always @(*) begin')
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combinational.append(' if (!%sclk && %sen) latch_%saddr <= %saddr;' % (prefix, prefix, prefix, prefix))
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combinational.append(' if (!%sclk && %sen) latch_%sdata <= %sdata;' % (prefix, prefix, prefix, prefix))
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combinational.append(' if (!%sclk) latch_%sen <= %sen;' % (prefix, prefix, prefix))
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combinational.append('end')
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combinational.append('always @(*)')
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combinational.append(' if (%sclk && latch_%sen)' % (prefix, prefix))
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combinational.append(' ram[latch_%saddr] <= latch_%sdata;' % (prefix, prefix))
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decl.append('reg [%d:0] ram [%d:0];' % (width-1, depth-1))
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decl.append('`ifdef RANDOMIZE_MEM_INIT')
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decl.append(' integer initvar;')
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decl.append(' initial begin')
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decl.append(' #0.002 begin end')
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decl.append(' for (initvar = 0; initvar < %d; initvar = initvar+1)' % depth)
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decl.append(' ram[initvar] = {%d {$random}};' % ((width-1)/32+1))
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for idx in range(nr):
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prefix = 'R%d_' % idx
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decl.append(' reg_%saddr = {%d {$random}};' % (prefix, ((addr_width-1)/32+1)))
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for idx in range(nrw):
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prefix = 'RW%d_' % idx
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decl.append(' reg_%saddr = {%d {$random}};' % (prefix, ((addr_width-1)/32+1)))
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decl.append(' end')
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decl.append('`endif')
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decl.append("integer i;")
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for idx in range(nw):
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prefix = 'W%d_' % idx
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pid = writeports[idx]
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sequential.append('always @(posedge %sclk)' % prefix)
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sequential.append(" if (%sen) begin" % prefix)
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for i in range(mask_seg):
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mask = ('if (%smask[%d]) ' % (prefix, i)) if pid in maskedports else ''
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ram_range = '%d:%d' % ((i+1)*mask_gran-1, i*mask_gran)
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sequential.append(" %sram[%saddr][%s] <= %sdata[%s];" % (mask, prefix, ram_range, prefix, ram_range))
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sequential.append(" end")
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for idx in range(nrw):
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pid = rwports[idx]
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prefix = 'RW%d_' % idx
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sequential.append('always @(posedge %sclk)' % prefix)
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sequential.append(" if (%sen && %swmode) begin" % (prefix, prefix))
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for i in range(mask_seg):
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mask = ('if (%swmask[%d]) ' % (prefix, i)) if pid in maskedports else ''
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ram_range = '%d:%d' % ((i+1)*mask_gran-1, i*mask_gran)
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sequential.append(" %sram[%saddr][%s] <= %swdata[%s];" % (mask, prefix, ram_range, prefix, ram_range))
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sequential.append(" end")
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body = "\
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%s\n\
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%s\n\
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%s\n" % ('\n '.join(decl), '\n '.join(sequential), '\n '.join(combinational))
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s = "\nmodule %s(\n\
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%s\n\
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);\n\
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\n\
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%s\
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\n\
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endmodule" % (name, ',\n '.join(port_spec), body)
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return s
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def main():
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if len(sys.argv) < 2:
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sys.exit('Please give a .conf file as input')
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for line in open(sys.argv[1]):
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print(gen_mem(*parse_line(line)))
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if __name__ == '__main__':
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main()
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138
scripts/vlsi_rom_gen
Executable file
138
scripts/vlsi_rom_gen
Executable file
@ -0,0 +1,138 @@
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#! /usr/bin/env python
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# See LICENSE.SiFive for license details.
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from __future__ import division
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from __future__ import print_function
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from __future__ import unicode_literals
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import doctest
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import sys
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import warnings
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from collections import namedtuple
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verilog_template = """
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module {name}(
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input clock,
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input oe,
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input me,
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input [{address_bits_minus_1}:0] address,
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output [{output_width_minus_1}:0] q
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);
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reg [{output_width_minus_1}:0] out;
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reg [{output_width_minus_1}:0] rom [0:{depth_minus_1}];
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// 1024 is the maximum length of $readmemh filename supported by Cadence Incisive
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reg [1024 * 8 - 1:0] path;
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integer i;
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initial begin
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`ifdef RANDOMIZE
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`ifdef RANDOMIZE_MEM_INIT
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for (i = 0; i < {depth}; i++) begin
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rom[i] = {{{num_random_blocks}{{$random}}}};
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end
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`endif
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`endif
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if (!$value$plusargs("maskromhex=%s", path)) begin
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path = "{rom_hex_file}";
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end
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$readmemh(path, rom);
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end
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always @(posedge clock) begin
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if (me) begin
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out <= rom[address];
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end
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end
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assign q = oe ? out : {output_width}'bZ;
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endmodule
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"""
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def gen_rom(name, width, depth, rom_hex_file):
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variables = {
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'name': name,
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'address_bits_minus_1': (depth - 1).bit_length() - 1,
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'depth': depth,
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'depth_minus_1': depth - 1,
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'output_width': width,
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'output_width_minus_1': width - 1,
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# $random in verilog returns 32 bits; compute how many times to repeat
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# $random in order to fill the width
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'num_random_blocks': (width - 1) // 32 + 1,
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'rom_hex_file': rom_hex_file,
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}
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return verilog_template.format(**variables)
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def iterate_by_n(it, n):
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"""Iterate over items in it, yielding n-tuples of successive items.
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>>> list(iterate_by_n([1, 2, 3, 4, 5, 6], n=2))
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[(1, 2), (3, 4), (5, 6)]
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>>> list(iterate_by_n([1, 2, 3, 4, 5, 6], n=3))
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[(1, 2, 3), (4, 5, 6)]
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>>> list(iterate_by_n([1, 2, 3, 4, 5, 6], n=4))
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Traceback (most recent call last):
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...
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ValueError: Iterable length not evenly divisible by 4
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"""
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it = iter(it)
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while True:
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batch = ()
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for i in range(n):
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try:
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batch += (next(it),)
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except StopIteration:
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if batch: # If this is not the first iteration
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raise ValueError(
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'Iterable length not evenly divisible by {}'.format(n)
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)
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else:
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raise
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yield batch
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def try_cast_int(x):
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try:
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return int(x)
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except ValueError:
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return x
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ROMParameters = namedtuple('ROMParameters', ['name', 'depth', 'width'])
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default_rom_parameters = ROMParameters(name='', depth=0, width=0)
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def parse_line(line):
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kwargs = {key: try_cast_int(val)
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for key, val in iterate_by_n(line.split(), 2)}
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rom_parameters = default_rom_parameters._replace(**kwargs)
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return rom_parameters._asdict()
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def main():
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if '--run-tests' in sys.argv:
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(failures, total) = doctest.testmod(verbose=True)
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sys.exit(1 if failures else 0)
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if len(sys.argv) < 2:
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sys.exit('Please give a .conf file as input')
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print('// This file created by ' + __file__)
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with open(sys.argv[1]) as fp:
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lines = fp.readlines()
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if len(lines) > 1:
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warnings.warn('vlsi_rom_gen detected multiple ROMs. ROM contents will be duplicated.')
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for line in lines:
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verilog = gen_rom(rom_hex_file=sys.argv[2],
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**parse_line(line))
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print(verilog)
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if __name__ == '__main__':
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main()
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