riscv/rocket-chip
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Pipeline D$ exception response into s2

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This commit is contained in:
Andrew Waterman
2017-04-14 23:57:32 -07:00
committed by Andrew Waterman
parent 657f4d4e0c
commit 6de6f38894
7 changed files with 21 additions and 27 deletions
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4
src/main/scala/rocket/SimpleHellaCacheIF.scala
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@ -130,8 +130,6 @@ class SimpleHellaCacheIF(implicit p: Parameters) extends Module
replayq.io.resp := io.cache.resp
io.requestor.resp := io.cache.resp
assert(!Reg(next = io.cache.req.fire()) ||
!(io.cache.xcpt.ma.ld || io.cache.xcpt.ma.st ||
io.cache.xcpt.pf.ld || io.cache.xcpt.pf.st),
assert(!RegNext(RegNext(io.cache.req.fire())) || !io.cache.s2_xcpt.asUInt.orR,
"SimpleHellaCacheIF exception")
}