riscv/rocket-chip
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Pipeline D$ exception response into s2

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This commit is contained in:
Andrew Waterman
2017-04-14 23:57:32 -07:00
committed by Andrew Waterman
parent 657f4d4e0c
commit 6de6f38894
7 changed files with 21 additions and 27 deletions
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3
src/main/scala/rocket/PTW.scala
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@ -78,7 +78,6 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
val count = Reg(UInt(width = log2Up(pgLevels)))
val s1_kill = Reg(next = Bool(false))
val resp_valid = Reg(next = Vec.fill(io.requestor.size)(Bool(false)))
val ae = Reg(next = io.mem.xcpt.ae.ld)
val resp_ae = Reg(Bool())
val r_req = Reg(new PTWReq)
@ -189,7 +188,7 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
resp_valid(r_req_dest) := true
}
}
when (ae) {
when (io.mem.s2_xcpt.ae.ld) {
resp_ae := true
state := s_ready
resp_valid(r_req_dest) := true